BX_CPU_C::Resolve64Mod0Base2(bxInstruction_c *i)
{
if (i->sibIndex() != 4)
RMAddr(i) = RDX + (BX_READ_64BIT_REG(i->sibIndex()) << i->sibScale());
else
RMAddr(i) = RDX;
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XADD_EwGwM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 4
Bit16u op1_16, op2_16, sum_16;
/* XADD dst(r/m), src(r)
* temp <-- src + dst | sum = op2 + op1
* src <-- dst | op2 = op1
* dst <-- tmp | op1 = sum
*/
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
sum_16 = op1_16 + op2_16;
write_RMW_virtual_word(sum_16);
/* and write destination into source */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16);
#else
BX_INFO(("XADD_EwGw: not supported on < 80486"));
UndefinedOpcode(i);
#endif
}
/* DB /7 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::FSTP_EXTENDED_REAL(bxInstruction_c *i)
{
#if BX_SUPPORT_FPU
BX_CPU_THIS_PTR prepareFPU(i);
clear_C1();
floatx80 save_reg = floatx80_default_nan; /* The masked response */
if (IS_TAG_EMPTY(0))
{
BX_CPU_THIS_PTR FPU_exception(FPU_EX_Stack_Underflow);
if (! (BX_CPU_THIS_PTR the_i387.is_IA_masked()))
return;
}
else
{
save_reg = BX_READ_FPU_REG(0);
}
write_virtual_tword(i->seg(), RMAddr(i), &save_reg);
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FSTP_EXTENDED_REAL: required FPU, configure --enable-fpu"));
#endif
}
/* 0F 0F /r 0D */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PI2FD_PqQq(bxInstruction_c *i)
{
BxPackedMmxRegister result, op;
BX_CPU_THIS_PTR prepareMMX();
/* op is a register or memory reference */
if (i->modC0()) {
op = BX_READ_MMX_REG(i->rm());
}
else {
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
MMXUQ(op) = read_virtual_qword(i->seg(), RMAddr(i));
}
float_status_t status_word;
prepare_softfloat_status_word(status_word, float_round_to_zero);
MMXUD0(result) =
int32_to_float32(MMXSD0(op), status_word);
MMXUD1(result) =
int32_to_float32(MMXSD1(op), status_word);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
}
/* 0F 0F /r B7 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PMULHRW_PqQq(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareMMX();
BxPackedMmxRegister op1 = BX_READ_MMX_REG(i->nnn()), op2, result;
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_MMX_REG(i->rm());
}
else {
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
MMXUQ(op2) = read_virtual_qword(i->seg(), RMAddr(i));
}
Bit32s product1 = Bit32s(MMXSW0(op1)) * Bit32s(MMXSW0(op2)) + 0x8000;
Bit32s product2 = Bit32s(MMXSW1(op1)) * Bit32s(MMXSW1(op2)) + 0x8000;
Bit32s product3 = Bit32s(MMXSW2(op1)) * Bit32s(MMXSW2(op2)) + 0x8000;
Bit32s product4 = Bit32s(MMXSW3(op1)) * Bit32s(MMXSW3(op2)) + 0x8000;
MMXUW0(result) = Bit16u(product1 >> 16);
MMXUW1(result) = Bit16u(product2 >> 16);
MMXUW2(result) = Bit16u(product3 >> 16);
MMXUW3(result) = Bit16u(product4 >> 16);
/* now write result back to destination */
BX_WRITE_MMX_REG(i->nnn(), result);
}
void BX_CPU_C::BSR_GqEq(bxInstruction_c *i)
{
/* for 64 bit operand size mode */
Bit64u op1_64, op2_64;
/* op2_64 is a register or memory reference */
if (i->modC0()) {
op2_64 = BX_READ_64BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_qword(i->seg(), RMAddr(i), &op2_64);
}
if (op2_64 == 0) {
assert_ZF(); /* op1_64 undefined */
return;
}
op1_64 = 63;
while ( (op2_64 & BX_CONST64(0x8000000000000000)) == 0 ) {
op1_64--;
op2_64 <<= 1;
}
SET_FLAGS_OSZAPC_RESULT_64(op1_64, BX_INSTR_BITSCAN64);
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
}
void BX_CPU_C::BSR_GdEd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32;
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
return;
}
op1_32 = 31;
while ( (op2_32 & 0x80000000) == 0 ) {
op1_32--;
op2_32 <<= 1;
}
SET_FLAGS_OSZAPC_RESULT_32(op1_32, BX_INSTR_BITSCAN32);
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void BX_CPU_C::BSR_GwEw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
/* op2_16 is a register or memory reference */
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
if (op2_16 == 0) {
assert_ZF(); /* op1_16 undefined */
return;
}
op1_16 = 15;
while ( (op2_16 & 0x8000) == 0 ) {
op1_16--;
op2_16 <<= 1;
}
SET_FLAGS_OSZAPC_RESULT_16(op1_16, BX_INSTR_BITSCAN16);
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
}
/* DD /1 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::FISTTP64(bxInstruction_c *i)
{
#if BX_SUPPORT_SSE >= 3
BX_CPU_THIS_PTR prepareFPU(i);
Bit64s save_reg = int64_indefinite; /* The masked response */
clear_C1();
if (IS_TAG_EMPTY(0))
{
BX_CPU_THIS_PTR FPU_exception(FPU_EX_Stack_Underflow);
if (! (BX_CPU_THIS_PTR the_i387.is_IA_masked()))
return;
}
else
{
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
save_reg = floatx80_to_int64_round_to_zero(BX_READ_FPU_REG(0), status);
if (BX_CPU_THIS_PTR FPU_exception(status.float_exception_flags))
return;
}
write_virtual_qword(i->seg(), RMAddr(i), (Bit64u)(save_reg));
BX_CPU_THIS_PTR the_i387.FPU_pop();
#else
BX_INFO(("FISTTP64: required SSE3, use --enable-sse option"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LDS_GwMp: invalid use of LDS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u reg_16, ds;
read_virtual_word(i->seg(), RMAddr(i), ®_16);
read_virtual_word(i->seg(), RMAddr(i) + 2, &ds);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
BX_WRITE_16BIT_REG(i->nnn(), reg_16);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::FLD_DOUBLE_REAL(bxInstruction_c *i)
{
#if BX_SUPPORT_FPU
BX_CPU_THIS_PTR prepareFPU(i);
float64 load_reg = read_virtual_qword(i->seg(), RMAddr(i));
clear_C1();
if (! IS_TAG_EMPTY(-1)) {
BX_CPU_THIS_PTR FPU_stack_overflow();
return;
}
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
// convert to floatx80 format
floatx80 result = float64_to_floatx80(load_reg, status);
if (BX_CPU_THIS_PTR FPU_exception(status.float_exception_flags))
return;
BX_CPU_THIS_PTR the_i387.FPU_push();
BX_WRITE_FPU_REG(result, 0);
#else
BX_INFO(("FLD_DOUBLE_REAL: required FPU, configure --enable-fpu"));
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_SwEw(bxInstruction_c *i)
{
Bit16u op2_16;
/* Attempt to load CS or nonexisting segment register */
if (i->nnn() >= 6 || i->nnn() == BX_SEG_REG_CS) {
BX_INFO(("MOV_EwSw: can't use this segment register %d", i->nnn()));
UndefinedOpcode(i);
}
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
op2_16 = read_virtual_word(i->seg(), RMAddr(i));
}
load_seg_reg(&BX_CPU_THIS_PTR sregs[i->nnn()], op2_16);
if (i->nnn() == BX_SEG_REG_SS) {
// MOV SS inhibits interrupts, debug exceptions and single-step
// trap exceptions until the execution boundary following the
// next instruction is reached.
// Same code as POP_SS()
BX_CPU_THIS_PTR inhibit_mask |= BX_INHIBIT_INTERRUPTS | BX_INHIBIT_DEBUG;
BX_CPU_THIS_PTR async_event = 1;
}
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPXCHG_EwGwM(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 4
Bit16u op1_16, op2_16, diff_16;
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
diff_16 = AX - op1_16;
SET_FLAGS_OSZAPC_SUB_16(AX, op1_16, diff_16);
if (diff_16 == 0) { // if accumulator == dest
// dest <-- src
op2_16 = BX_READ_16BIT_REG(i->nnn());
write_RMW_virtual_word(op2_16);
}
else {
// accumulator <-- dest
AX = op1_16;
}
#else
BX_INFO(("CMPXCHG_EwGw: not supported for cpu-level <= 3"));
UndefinedOpcode(i);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOV_GwEwM(bxInstruction_c *i)
{
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u val16 = read_virtual_word(i->seg(), RMAddr(i));
BX_WRITE_16BIT_REG(i->nnn(), val16);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FCOM_DOUBLE_REAL(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareFPU(i);
int pop_stack = i->nnn() & 1, rc;
RMAddr(i) = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
float64 load_reg = read_virtual_qword(i->seg(), RMAddr(i));
BX_CPU_THIS_PTR FPU_update_last_instruction(i);
clear_C1();
if (IS_TAG_EMPTY(0))
{
FPU_exception(FPU_EX_Stack_Underflow);
setcc(FPU_SW_C0|FPU_SW_C2|FPU_SW_C3);
if(BX_CPU_THIS_PTR the_i387.is_IA_masked())
{
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
BX_NEXT_INSTR(i);
}
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
floatx80 a = BX_READ_FPU_REG(0);
if (floatx80_is_nan(a) || floatx80_is_unsupported(a) || float64_is_nan(load_reg)) {
rc = float_relation_unordered;
float_raise(status, float_flag_invalid);
}
else {
rc = floatx80_compare(a, float64_to_floatx80(load_reg, status), status);
}
setcc(status_word_flags_fpu_compare(rc));
if (! FPU_exception(status.float_exception_flags)) {
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
}
BX_NEXT_INSTR(i);
}
/* 66 0F 3A 62 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRM_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2, result;
Bit8u imm8 = i->Ib();
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_XMM_REG(i->rm());
}
else {
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
}
// compare all pairs of Ai, Bj
bx_bool BoolRes[16][16];
compare_strings(BoolRes, op1, op2, imm8);
unsigned num_elements = (imm8 & 0x1) ? 8 : 16;
unsigned len1 = find_eos(op1, imm8);
unsigned len2 = find_eos(op2, imm8);
Bit16u result2 = aggregate(BoolRes, len1, len2, imm8);
// As defined by imm8[6], result2 is then either stored to the least
// significant bits of XMM0 (zero extended to 128 bits) or expanded
// into a byte/word-mask and then stored to XMM0
if (imm8 & 0x40) {
if (num_elements == 8) {
for (int index = 0; index < 8; index++)
result.xmm16u(index) = (result2 & (1<<index)) ? 0xffff : 0;
}
else { // num_elements = 16
for (int index = 0; index < 16; index++)
result.xmmubyte(index) = (result2 & (1<<index)) ? 0xff : 0;
}
}
else {
result.xmm64u(1) = 0;
result.xmm64u(0) = (Bit64u) result2;
}
Bit32u flags = 0;
if (result2 != 0) flags |= EFlagsCFMask;
if (len1 < num_elements) flags |= EFlagsSFMask;
if (len2 < num_elements) flags |= EFlagsZFMask;
if (result2 & 0x1)
flags |= EFlagsOFMask;
setEFlagsOSZAPC(flags);
BX_WRITE_XMM_REG(0, result); /* store result XMM0 */
#else
BX_INFO(("PCMPISTRM_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
#endif
}
void BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LSS_GqMp: invalid use of LSS, must be memory reference!"));
UndefinedOpcode(i);
}
Bit64u reg_64;
Bit16u ss;
read_virtual_qword(i->seg(), RMAddr(i), ®_64);
read_virtual_word(i->seg(), RMAddr(i) + 8, &ss);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
BX_WRITE_64BIT_REG(i->nnn(), reg_64);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PUSH_EdM(bxInstruction_c *i)
{
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_32 = read_virtual_dword(i->seg(), RMAddr(i));
push_32(op1_32);
}
void BX_CPU_C::LES_GdMp(bxInstruction_c *i)
{
if (i->modC0()) {
BX_DEBUG(("LES_GdMp: invalid use of LES, must be memory reference!"));
UndefinedOpcode(i);
}
Bit16u es;
Bit32u reg_32;
read_virtual_dword(i->seg(), RMAddr(i), ®_32);
read_virtual_word(i->seg(), RMAddr(i) + 4, &es);
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FIST_DWORD_INTEGER(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareFPU(i);
RMAddr(i) = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
FPU_update_last_instruction(i);
Bit16u x87_sw = FPU_PARTIAL_STATUS;
Bit32s save_reg = int32_indefinite; /* The masked response */
int pop_stack = i->nnn() & 1;
clear_C1();
if (IS_TAG_EMPTY(0))
{
FPU_exception(FPU_EX_Stack_Underflow);
if (! BX_CPU_THIS_PTR the_i387.is_IA_masked())
BX_NEXT_INSTR(i);
}
else
{
float_status_t status =
FPU_pre_exception_handling(BX_CPU_THIS_PTR the_i387.get_control_word());
save_reg = floatx80_to_int32(BX_READ_FPU_REG(0), status);
if (FPU_exception(status.float_exception_flags, 1))
BX_NEXT_INSTR(i);
}
// store to the memory might generate an exception, in this case origial FPU_SW must be kept
swap_values16u(x87_sw, FPU_PARTIAL_STATUS);
write_virtual_dword(i->seg(), RMAddr(i), (Bit32u)(save_reg));
FPU_PARTIAL_STATUS = x87_sw;
if (pop_stack)
BX_CPU_THIS_PTR the_i387.FPU_pop();
BX_NEXT_INSTR(i);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVSX_GwEbM(bxInstruction_c *i)
{
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit8u op2_8 = read_virtual_byte(i->seg(), RMAddr(i));
/* sign extend byte op2 into word op1 */
BX_WRITE_16BIT_REG(i->nnn(), (Bit8s) op2_8);
}
/* 66 0F 3A 63 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::PCMPISTRI_VdqWdqIb(bxInstruction_c *i)
{
#if (BX_SUPPORT_SSE >= 5) || (BX_SUPPORT_SSE >= 4 && BX_SUPPORT_SSE_EXTENSION > 0)
BX_CPU_THIS_PTR prepareSSE();
BxPackedXmmRegister op1 = BX_READ_XMM_REG(i->nnn()), op2;
Bit8u imm8 = i->Ib();
/* op2 is a register or memory reference */
if (i->modC0()) {
op2 = BX_READ_XMM_REG(i->rm());
}
else {
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
/* pointer, segment address pair */
readVirtualDQwordAligned(i->seg(), RMAddr(i), (Bit8u *) &op2);
}
// compare all pairs of Ai, Bj
bx_bool BoolRes[16][16];
compare_strings(BoolRes, op1, op2, imm8);
unsigned num_elements = (imm8 & 0x1) ? 8 : 16;
int index;
unsigned len1 = find_eos(op1, imm8);
unsigned len2 = find_eos(op2, imm8);
Bit16u result2 = aggregate(BoolRes, len1, len2, imm8);
// The index of the first (or last, according to imm8[6]) set bit of result2
// is returned to ECX. If no bits are set in IntRes2, ECX is set to 16 (8)
if (imm8 & 0x40) {
// The index returned to ECX is of the MSB in result2
for (index=num_elements-1; index>=0; index--)
if (result2 & (1<<index)) break;
if (index < 0) index = num_elements;
}
else {
// The index returned to ECX is of the LSB in result2
for (index=0; index<(int)num_elements; index++)
if (result2 & (1<<index)) break;
}
RCX = index;
Bit32u flags = 0;
if (result2 != 0) flags |= EFlagsCFMask;
if (len1 < num_elements) flags |= EFlagsSFMask;
if (len2 < num_elements) flags |= EFlagsZFMask;
if (result2 & 0x1)
flags |= EFlagsOFMask;
setEFlagsOSZAPC(flags);
#else
BX_INFO(("PCMPISTRI_VdqWdqIb: required SSE4.2, use --enable-sse and --enable-sse-extension options"));
UndefinedOpcode(i);
#endif
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::CMP_EwIwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16 = i->Iw(), diff_16;
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_virtual_word(i->seg(), RMAddr(i));
diff_16 = op1_16 - op2_16;
SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EqM(bxInstruction_c *i)
{
Bit64u op1_64;
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_64 = read_RMW_virtual_qword_64(i->seg(), RMAddr(i));
op1_64 = ~op1_64;
write_RMW_virtual_qword(op1_64);
}
void BX_CPU_C::LEA_GdM(bxInstruction_c *i)
{
if (i->modC0()) {
BX_INFO(("LEA_GdM: op2 is a register"));
UndefinedOpcode(i);
}
/* write effective address of op2 in op1 */
BX_WRITE_32BIT_REGZ(i->nnn(), RMAddr(i));
}
void BX_CPU_C::MOV_EbIb(bxInstruction_c *i)
{
Bit8u op2 = i->Ib();
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
else {
write_virtual_byte(i->seg(), RMAddr(i), &op2);
}
}
/* DF /4 */
void BX_CPP_AttrRegparmN(1) BX_CPU_C::FBLD_PACKED_BCD(bxInstruction_c *i)
{
#if BX_SUPPORT_FPU
BX_CPU_THIS_PTR prepareFPU(i);
// read packed bcd from memory
Bit16u hi2 = read_virtual_word (i->seg(), RMAddr(i) + 8);
Bit64u lo8 = read_virtual_qword(i->seg(), RMAddr(i));
clear_C1();
if (! IS_TAG_EMPTY(-1))
{
BX_CPU_THIS_PTR FPU_stack_overflow();
return;
}
// convert packed BCD to 64-bit integer
Bit64s scale = 1;
Bit64s val64 = 0;
for (int n = 0; n < 16; n++)
{
val64 += (lo8 & 0x0f) * scale;
lo8 >>= 4;
scale *= 10;
}
val64 += (hi2 & 0x0f) * scale;
val64 += ((hi2>>4) & 0x0f) * scale * 10;
floatx80 result = int64_to_floatx80(val64);
if (hi2 & 0x8000) // set negative
floatx80_chs(result);
BX_CPU_THIS_PTR the_i387.FPU_push();
BX_WRITE_FPU_REG(result, 0);
#else
BX_INFO(("FBLD_PACKED_BCD: required FPU, configure --enable-fpu"));
#endif
}
/* DF /4 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::FBLD_PACKED_BCD(bxInstruction_c *i)
{
BX_CPU_THIS_PTR prepareFPU(i);
RMAddr(i) = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit16u hi2 = read_virtual_word(i->seg(), (RMAddr(i) + 8) & i->asize_mask());
Bit64u lo8 = read_virtual_qword(i->seg(), RMAddr(i));
FPU_update_last_instruction(i);
clear_C1();
if (! IS_TAG_EMPTY(-1))
{
FPU_stack_overflow();
BX_NEXT_INSTR(i);
}
// convert packed BCD to 64-bit integer
Bit64s scale = 1;
Bit64s val64 = 0;
for (int n = 0; n < 16; n++)
{
val64 += (lo8 & 0x0f) * scale;
lo8 >>= 4;
scale *= 10;
}
val64 += (hi2 & 0x0f) * scale;
val64 += ((hi2>>4) & 0x0f) * scale * 10;
floatx80 result = int64_to_floatx80(val64);
if (hi2 & 0x8000) // set negative
floatx80_chs(result);
BX_CPU_THIS_PTR the_i387.FPU_push();
BX_WRITE_FPU_REG(result, 0);
BX_NEXT_INSTR(i);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::XCHG_EwGwM(bxInstruction_c *i)
{
Bit16u op1_16, op2_16;
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
write_RMW_virtual_word(op2_16);
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::DEC_EwM(bxInstruction_c *i)
{
Bit16u op1_16;
BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_16 = read_RMW_virtual_word(i->seg(), RMAddr(i));
op1_16--;
write_RMW_virtual_word(op1_16);
SET_FLAGS_OSZAPC_DEC_16(op1_16);
}
