static void delay_slot(UINT16 startpc)
{
tms.op = ROPCODE();
tms32051_opcode_table[tms.op >> 8]();
while (tms.pc - startpc < 2)
{
tms.op = ROPCODE();
tms32051_opcode_table[tms.op >> 8]();
}
}
static void delay_slot(tms32051_state *cpustate, UINT16 startpc)
{
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
while (cpustate->pc - startpc < 2)
{
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
}
}
INLINE void CHANGE_PC(UINT32 newpc)
{
sharc.pc = newpc;
sharc.daddr = newpc;
sharc.faddr = newpc+1;
sharc.nfaddr = newpc+2;
// next instruction to be executed
sharc.decode_opcode = ROPCODE(sharc.daddr);
// next instruction to be decoded
sharc.fetch_opcode = ROPCODE(sharc.faddr);
}
static int t11_execute(int cycles)
{
t11_ICount = cycles;
t11_ICount -= t11.interrupt_cycles;
t11.interrupt_cycles = 0;
if (t11.wait_state)
{
t11_ICount = 0;
goto getout;
}
do
{
t11.ppc = t11.reg[7]; /* copy PC to previous PC */
CALL_DEBUGGER(PCD);
t11.op = ROPCODE();
(*opcode_table[t11.op >> 3])();
} while (t11_ICount > 0);
getout:
t11_ICount -= t11.interrupt_cycles;
t11.interrupt_cycles = 0;
return cycles - t11_ICount;
}
static CPU_EXECUTE( t11 )
{
t11_state *cpustate = get_safe_token(device);
t11_check_irqs(cpustate);
if (cpustate->wait_state)
{
cpustate->icount = 0;
goto getout;
}
do
{
UINT16 op;
cpustate->ppc = cpustate->reg[7]; /* copy PC to previous PC */
debugger_instruction_hook(device, cpustate->PCD);
op = ROPCODE(cpustate);
(*opcode_table[op >> 3])(cpustate, op);
} while (cpustate->icount > 0);
getout:
;
}
static int tms_execute(int num_cycles)
{
tms_icount = num_cycles;
while(tms_icount > 0)
{
UINT16 ppc;
// handle block repeat
if (tms.pmst.braf)
{
if (tms.pc == tms.paer)
{
if (tms.brcr > 0)
{
CHANGE_PC(tms.pasr);
}
tms.brcr--;
if (tms.brcr <= 0)
{
tms.pmst.braf = 0;
}
}
}
ppc = tms.pc;
CALL_DEBUGGER(tms.pc);
tms.op = ROPCODE();
tms32051_opcode_table[tms.op >> 8]();
// handle single repeat
if (tms.rptc > 0)
{
if (ppc == tms.rpt_end)
{
CHANGE_PC(tms.rpt_start);
tms.rptc--;
}
}
else
{
tms.rptc = 0;
}
tms.timer.psc--;
if (tms.timer.psc <= 0)
{
tms.timer.psc = tms.timer.tddr;
tms.timer.tim--;
if (tms.timer.tim <= 0)
{
// reset timer
tms.timer.tim = tms.timer.prd;
tms_interrupt(INTERRUPT_TINT);
}
}
}
return num_cycles - tms_icount;
}
unsigned dasmmips3(char *buffer, unsigned pc)
{
UINT32 op = ROPCODE(pc);
int rs = (op >> 21) & 31;
int rt = (op >> 16) & 31;
int rd = (op >> 11) & 31;
int shift = (op >> 6) & 31;
switch (op >> 26)
{
case 0x00: /* SPECIAL */
switch (op & 63)
{
case 0x00: if (op == 0)
sprintf(buffer, "nop");
else
sprintf(buffer, "sll %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x01: sprintf(buffer, "mov%c %s,%s,%d", ((op >> 16) & 1) ? 't' : 'f', reg[rd], reg[rt], (op >> 18) & 7); break;
case 0x02: sprintf(buffer, "srl %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x03: sprintf(buffer, "sra %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x04: sprintf(buffer, "sllv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x06: sprintf(buffer, "srlv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x07: sprintf(buffer, "srav %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x08: sprintf(buffer, "jr %s", reg[rs]); break;
case 0x09: if (rd == 31)
sprintf(buffer, "jalr %s", reg[rs]);
else
sprintf(buffer, "jalr %s,%s", reg[rs], reg[rd]); break;
case 0x0a: sprintf(buffer, "movz %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x0b: sprintf(buffer, "movn %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x0c: sprintf(buffer, "syscall"); break;
case 0x0d: sprintf(buffer, "break"); break;
case 0x0f: sprintf(buffer, "sync"); break;
case 0x10: sprintf(buffer, "mfhi %s", reg[rd]); break;
case 0x11: sprintf(buffer, "mthi %s", reg[rs]); break;
case 0x12: sprintf(buffer, "mflo %s", reg[rd]); break;
case 0x13: sprintf(buffer, "mtlo %s", reg[rs]); break;
case 0x14: sprintf(buffer, "dsllv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x16: sprintf(buffer, "dsrlv %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x17: sprintf(buffer, "dsrav %s,%s,%s", reg[rd], reg[rt], reg[rs]); break;
case 0x18: sprintf(buffer, "mult %s,%s", reg[rs], reg[rt]); break;
case 0x19: sprintf(buffer, "multu %s,%s", reg[rs], reg[rt]); break;
case 0x1a: sprintf(buffer, "div %s,%s", reg[rs], reg[rt]); break;
case 0x1b: sprintf(buffer, "divu %s,%s", reg[rs], reg[rt]); break;
case 0x1c: sprintf(buffer, "dmult %s,%s", reg[rs], reg[rt]); break;
case 0x1d: sprintf(buffer, "dmultu %s,%s", reg[rs], reg[rt]); break;
case 0x1e: sprintf(buffer, "ddiv %s,%s", reg[rs], reg[rt]); break;
case 0x1f: sprintf(buffer, "ddivu %s,%s", reg[rs], reg[rt]); break;
case 0x20: sprintf(buffer, "add %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x21: sprintf(buffer, "addu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x22: sprintf(buffer, "sub %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x23: sprintf(buffer, "subu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x24: sprintf(buffer, "and %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x25: sprintf(buffer, "or %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x26: sprintf(buffer, "xor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x27: sprintf(buffer, "nor %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2a: sprintf(buffer, "slt %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2b: sprintf(buffer, "sltu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2c: sprintf(buffer, "dadd %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2d: sprintf(buffer, "daddu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2e: sprintf(buffer, "dsub %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x2f: sprintf(buffer, "dsubu %s,%s,%s", reg[rd], reg[rs], reg[rt]); break;
case 0x30: sprintf(buffer, "tge %s,%s", reg[rs], reg[rt]); break;
case 0x31: sprintf(buffer, "tgeu %s,%s", reg[rs], reg[rt]); break;
case 0x32: sprintf(buffer, "tlt %s,%s", reg[rs], reg[rt]); break;
case 0x33: sprintf(buffer, "tltu %s,%s", reg[rs], reg[rt]); break;
case 0x34: sprintf(buffer, "teq %s,%s", reg[rs], reg[rt]); break;
case 0x36: sprintf(buffer, "tne %s,%s", reg[rs], reg[rt]); break;
case 0x38: sprintf(buffer, "dsll %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3a: sprintf(buffer, "dsrl %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3b: sprintf(buffer, "dsra %s,%s,%d", reg[rd], reg[rt], shift); break;
case 0x3c: sprintf(buffer, "dsll %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3e: sprintf(buffer, "dsrl %s,%s,%d", reg[rd], reg[rt], shift+32); break;
case 0x3f: sprintf(buffer, "dsra %s,%s,%d", reg[rd], reg[rt], shift+32); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x01: /* REGIMM */
switch ((op >> 16) & 31)
{
case 0x00: sprintf(buffer, "bltz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x01: sprintf(buffer, "bgez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x02: sprintf(buffer, "bltzl %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x03: sprintf(buffer, "bgezl %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x08: sprintf(buffer, "tgei %s,%s", reg[rs], signed_16bit(op)); break;
case 0x09: sprintf(buffer, "tgeiu %s,%s", reg[rs], signed_16bit(op)); break;
case 0x0a: sprintf(buffer, "tlti %s,%s", reg[rs], signed_16bit(op)); break;
case 0x0b: sprintf(buffer, "tltiu %s,%s", reg[rs], signed_16bit(op)); break;
case 0x0c: sprintf(buffer, "teqi %s,%s", reg[rs], signed_16bit(op)); break;
case 0x0e: sprintf(buffer, "tnei %s,%s", reg[rs], signed_16bit(op)); break;
case 0x10: sprintf(buffer, "bltzal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x11: sprintf(buffer, "bgezal %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x12: sprintf(buffer, "bltzall %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2));break;
case 0x13: sprintf(buffer, "bgezall %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2));break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
break;
case 0x02: sprintf(buffer, "j $%08x", (pc & 0xf0000000) | ((op & 0x0fffffff) << 2)); break;
case 0x03: sprintf(buffer, "jal $%08x", (pc & 0xf0000000) | ((op & 0x0fffffff) << 2)); break;
case 0x04: if (rs == 0 && rt == 0)
sprintf(buffer, "b $%08x", pc + 4 + ((INT16)op << 2));
else
sprintf(buffer, "beq %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x05: sprintf(buffer, "bne %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x06: sprintf(buffer, "blez %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x07: sprintf(buffer, "bgtz %s,$%08x", reg[rs], pc + 4 + ((INT16)op << 2)); break;
case 0x08: sprintf(buffer, "addi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x09: sprintf(buffer, "addiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0a: sprintf(buffer, "slti %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0b: sprintf(buffer, "sltiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x0c: sprintf(buffer, "andi %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0d: sprintf(buffer, "ori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0e: sprintf(buffer, "xori %s,%s,$%04x", reg[rt], reg[rs], (UINT16)op); break;
case 0x0f: sprintf(buffer, "lui %s,$%04x", reg[rt], (UINT16)op); break;
case 0x10: dasm_cop0(pc, op, buffer); break;
case 0x11: dasm_cop1(pc, op, buffer); break;
case 0x12: dasm_cop2(pc, op, buffer); break;
case 0x13: dasm_cop1x(pc, op, buffer); break;
case 0x14: sprintf(buffer, "beql %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x15: sprintf(buffer, "bnel %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x16: sprintf(buffer, "blezl %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x17: sprintf(buffer, "bgtzl %s,%s,$%08x", reg[rs], reg[rt], pc + 4 + ((INT16)op << 2));break;
case 0x18: sprintf(buffer, "daddi %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x19: sprintf(buffer, "daddiu %s,%s,%s", reg[rt], reg[rs], signed_16bit(op)); break;
case 0x1a: sprintf(buffer, "ldl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x1b: sprintf(buffer, "ldr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x20: sprintf(buffer, "lb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x21: sprintf(buffer, "lh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x22: sprintf(buffer, "lwl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x23: sprintf(buffer, "lw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x24: sprintf(buffer, "lbu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x25: sprintf(buffer, "lhu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x26: sprintf(buffer, "lwr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x27: sprintf(buffer, "lwu %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x28: sprintf(buffer, "sb %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x29: sprintf(buffer, "sh %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2a: sprintf(buffer, "swl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2b: sprintf(buffer, "sw %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2c: sprintf(buffer, "sdl %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2d: sprintf(buffer, "sdr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2e: sprintf(buffer, "swr %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x2f: sprintf(buffer, "cache %s(%s)", reg[rs], signed_16bit(op)); break;
case 0x30: sprintf(buffer, "ll %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x31: sprintf(buffer, "lwc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x32: sprintf(buffer, "lwc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x33: sprintf(buffer, "pref $%x,%s(%s)", rt, signed_16bit(op), reg[rs]); break;
case 0x34: sprintf(buffer, "lld %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x35: sprintf(buffer, "ldc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x36: sprintf(buffer, "ldc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x37: sprintf(buffer, "ld %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x38: sprintf(buffer, "sc %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x39: sprintf(buffer, "swc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3a: sprintf(buffer, "swc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3c: sprintf(buffer, "scd %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
case 0x3d: sprintf(buffer, "sdc1 %s,%s(%s)", cpreg[1][rt], signed_16bit(op), reg[rs]); break;
case 0x3e: sprintf(buffer, "sdc2 %s,%s(%s)", cpreg[2][rt], signed_16bit(op), reg[rs]); break;
case 0x3f: sprintf(buffer, "sd %s,%s(%s)", reg[rt], signed_16bit(op), reg[rs]); break;
default: sprintf(buffer, "dc.l $%08x [invalid]", op); break;
}
return 4;
}
static CPU_EXECUTE( tms )
{
tms32051_state *cpustate = get_safe_token(device);
while(cpustate->icount > 0)
{
UINT16 ppc;
// handle block repeat
if (cpustate->pmst.braf)
{
if (cpustate->pc == cpustate->paer)
{
if (cpustate->brcr > 0)
{
CHANGE_PC(cpustate, cpustate->pasr);
}
cpustate->brcr--;
if (cpustate->brcr <= 0)
{
cpustate->pmst.braf = 0;
}
}
}
ppc = cpustate->pc;
debugger_instruction_hook(device, cpustate->pc);
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
// handle single repeat
if (cpustate->rptc > 0)
{
if (ppc == cpustate->rpt_end)
{
CHANGE_PC(cpustate, cpustate->rpt_start);
cpustate->rptc--;
}
}
else
{
cpustate->rptc = 0;
}
cpustate->timer.psc--;
if (cpustate->timer.psc <= 0)
{
cpustate->timer.psc = cpustate->timer.tddr;
cpustate->timer.tim--;
if (cpustate->timer.tim <= 0)
{
// reset timer
cpustate->timer.tim = cpustate->timer.prd;
tms_interrupt(cpustate, INTERRUPT_TINT);
}
}
}
}
static unsigned dasmjag(int variant, char *buffer, unsigned pc, const UINT8 *oprom)
{
UINT32 flags = 0;
int op = ROPCODE(0);
int reg1 = (op >> 5) & 31;
int reg2 = op & 31;
int size = 2;
pc += 2;
switch (op >> 10)
{
case 0: sprintf(buffer, "add r%d,r%d", reg1, reg2); break;
case 1: sprintf(buffer, "addc r%d,r%d", reg1, reg2); break;
case 2: sprintf(buffer, "addq $%x,r%d", convert_zero[reg1], reg2); break;
case 3: sprintf(buffer, "addqt $%x,r%d", convert_zero[reg1], reg2); break;
case 4: sprintf(buffer, "sub r%d,r%d", reg1, reg2); break;
case 5: sprintf(buffer, "subc r%d,r%d", reg1, reg2); break;
case 6: sprintf(buffer, "subq $%x,r%d", convert_zero[reg1], reg2); break;
case 7: sprintf(buffer, "subqt $%x,r%d", convert_zero[reg1], reg2); break;
case 8: sprintf(buffer, "neg r%d", reg2); break;
case 9: sprintf(buffer, "and r%d,r%d", reg1, reg2); break;
case 10: sprintf(buffer, "or r%d,r%d", reg1, reg2); break;
case 11: sprintf(buffer, "xor r%d,r%d", reg1, reg2); break;
case 12: sprintf(buffer, "not r%d", reg2); break;
case 13: sprintf(buffer, "btst $%x,r%d", reg1, reg2); break;
case 14: sprintf(buffer, "bset $%x,r%d", reg1, reg2); break;
case 15: sprintf(buffer, "bclr $%x,r%d", reg1, reg2); break;
case 16: sprintf(buffer, "mult r%d,r%d", reg1, reg2); break;
case 17: sprintf(buffer, "imult r%d,r%d", reg1, reg2); break;
case 18: sprintf(buffer, "imultn r%d,r%d", reg1, reg2); break;
case 19: sprintf(buffer, "resmac r%d", reg2); break;
case 20: sprintf(buffer, "imacn r%d,r%d", reg1, reg2); break;
case 21: sprintf(buffer, "div r%d,r%d", reg1, reg2); break;
case 22: sprintf(buffer, "abs r%d", reg2); break;
case 23: sprintf(buffer, "sh r%d,r%d", reg1, reg2); break;
case 24: sprintf(buffer, "shlq $%x,r%d", 32 - convert_zero[reg1], reg2); break;
case 25: sprintf(buffer, "shrq $%x,r%d", convert_zero[reg1], reg2); break;
case 26: sprintf(buffer, "sha r%d,r%d", reg1, reg2); break;
case 27: sprintf(buffer, "sharq $%x,r%d", convert_zero[reg1], reg2); break;
case 28: sprintf(buffer, "ror r%d,r%d", reg1, reg2); break;
case 29: sprintf(buffer, "rorq $%x,r%d", convert_zero[reg1], reg2); break;
case 30: sprintf(buffer, "cmp r%d,r%d", reg1, reg2); break;
case 31: sprintf(buffer, "cmpq %s,r%d", signed_16bit((INT16)(reg1 << 11) >> 11), reg2);break;
case 32: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, "sat8 r%d", reg2);
else
sprintf(buffer, "subqmod $%x,r%d", convert_zero[reg1], reg2);
break;
case 33: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, "sat16 r%d", reg2);
else
sprintf(buffer, "sat16s r%d", reg2);
break;
case 34: sprintf(buffer, "move r%d,r%d", reg1, reg2); break;
case 35: sprintf(buffer, "moveq %d,r%d", reg1, reg2); break;
case 36: sprintf(buffer, "moveta r%d,r%d", reg1, reg2); break;
case 37: sprintf(buffer, "movefa r%d,r%d", reg1, reg2); break;
case 38: sprintf(buffer, "movei $%x,r%d", ROPCODE(2) | (ROPCODE(4)<<16), reg2); size = 6; break;
case 39: sprintf(buffer, "loadb (r%d),r%d", reg1, reg2); break;
case 40: sprintf(buffer, "loadw (r%d),r%d", reg1, reg2); break;
case 41: sprintf(buffer, "load (r%d),r%d", reg1, reg2); break;
case 42: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, "loadp (r%d),r%d", reg1, reg2);
else
sprintf(buffer, "sat32s r%d", reg2);
break;
case 43: sprintf(buffer, "load (r14+$%x),r%d", convert_zero[reg1]*4, reg2);break;
case 44: sprintf(buffer, "load (r15+$%x),r%d", convert_zero[reg1]*4, reg2);break;
case 45: sprintf(buffer, "storeb r%d,(r%d)", reg2, reg1); break;
case 46: sprintf(buffer, "storew r%d,(r%d)", reg2, reg1); break;
case 47: sprintf(buffer, "store r%d,(r%d)", reg2, reg1); break;
case 48: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, "storep r%d,(r%d)", reg2, reg1);
else
sprintf(buffer, "mirror r%d", reg2);
break;
case 49: sprintf(buffer, "store r%d,(r14+$%x)", reg2, convert_zero[reg1]*4);break;
case 50: sprintf(buffer, "store r%d,(r15+$%x)", reg2, convert_zero[reg1]*4);break;
case 51: sprintf(buffer, "move pc,r%d", reg2); break;
case 52: sprintf(buffer, "jump %s(r%d)", condition[reg2], reg1); break;
case 53: sprintf(buffer, "jr %s%08X", condition[reg2], pc + ((INT8)(reg1 << 3) >> 2)); break;
case 54: sprintf(buffer, "mmult r%d,r%d", reg1, reg2); break;
case 55: sprintf(buffer, "mtoi r%d,r%d", reg1, reg2); break;
case 56: sprintf(buffer, "normi r%d,r%d", reg1, reg2); break;
case 57: sprintf(buffer, "nop"); break;
case 58: sprintf(buffer, "load (r14+r%d),r%d", reg1, reg2); break;
case 59: sprintf(buffer, "load (r15+r%d),r%d", reg1, reg2); break;
case 60: sprintf(buffer, "store r%d,(r14+r%d)", reg2, reg1); break;
case 61: sprintf(buffer, "store r%d,(r15+r%d)", reg2, reg1); break;
case 62: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, "sat24 r%d", reg2);
else
sprintf(buffer, "illegal");
break;
case 63: if (variant == JAGUAR_VARIANT_GPU)
sprintf(buffer, reg1 ?
"unpack r%d" :
"pack r%d", reg2);
else
sprintf(buffer, "addqmod $%x,r%d", convert_zero[reg1], reg2);
break;
}
return size | flags | DASMFLAG_SUPPORTED;
}
static int sharc_execute(int cycles)
{
sharc_icount = cycles;
if (sharc.idle && sharc.irq_active == 0)
{
// handle pending DMA transfers
if (dmaop_cycles > 0)
{
dmaop_cycles -= cycles;
if (dmaop_cycles <= 0)
{
dmaop_cycles = 0;
dma_op(dmaop_src, dmaop_dst, dmaop_src_modifier, dmaop_dst_modifier, dmaop_src_count, dmaop_dst_count, dmaop_pmode);
if (dmaop_chain_ptr != 0)
{
schedule_chained_dma_op(dmaop_channel, dmaop_chain_ptr, dmaop_chained_direction);
}
}
}
sharc_icount = 0;
CALL_MAME_DEBUG;
return cycles;
}
if (sharc.irq_active != 0)
{
check_interrupts();
sharc.idle = 0;
}
// fill the initial pipeline
// next executed instruction
sharc.opcode = ROPCODE(sharc.daddr);
sharc.opcode_handler = sharc_op[(sharc.opcode >> 39) & 0x1ff];
// next decoded instruction
sharc.fetch_opcode = ROPCODE(sharc.faddr);
while (sharc_icount > 0 && !sharc.idle)
{
sharc.pc = sharc.daddr;
sharc.daddr = sharc.faddr;
sharc.faddr = sharc.nfaddr;
sharc.nfaddr++;
sharc.decode_opcode = sharc.fetch_opcode;
// fetch next instruction
sharc.fetch_opcode = ROPCODE(sharc.faddr);
CALL_MAME_DEBUG;
// handle looping
if (sharc.pc == (sharc.laddr & 0xffffff))
{
switch (sharc.laddr >> 30)
{
case 0: // arithmetic condition-based
{
int condition = (sharc.laddr >> 24) & 0x1f;
if (DO_CONDITION_CODE(condition))
{
POP_LOOP();
POP_PC();
}
else
{
CHANGE_PC(TOP_PC());
}
break;
}
case 1: // counter-based, length 1
{
//fatalerror("SHARC: counter-based loop, length 1 at %08X", sharc.pc);
//break;
}
case 2: // counter-based, length 2
{
//fatalerror("SHARC: counter-based loop, length 2 at %08X", sharc.pc);
//break;
}
case 3: // counter-based, length >2
{
--sharc.lcstack[sharc.lstkp];
--sharc.curlcntr;
if (sharc.curlcntr == 0)
{
POP_LOOP();
POP_PC();
}
else
{
CHANGE_PC(TOP_PC());
}
}
}
}
// execute current instruction
sharc.opcode_handler();
// decode next instruction
sharc.opcode = sharc.decode_opcode;
sharc.opcode_handler = sharc_op[(sharc.opcode >> 39) & 0x1ff];
// System register latency effect
if (systemreg_latency_cycles > 0)
{
--systemreg_latency_cycles;
if (systemreg_latency_cycles <= 0)
{
systemreg_write_latency_effect();
}
}
// IOP register latency effect
if (iop_latency_cycles > 0)
{
--iop_latency_cycles;
if (iop_latency_cycles <= 0)
{
iop_write_latency_effect();
}
}
// DMA transfer
if (dmaop_cycles > 0)
{
--dmaop_cycles;
if (dmaop_cycles <= 0)
{
dma_op(dmaop_src, dmaop_dst, dmaop_src_modifier, dmaop_dst_modifier, dmaop_src_count, dmaop_dst_count, dmaop_pmode);
if (dmaop_chain_ptr != 0)
{
schedule_chained_dma_op(dmaop_channel, dmaop_chain_ptr, dmaop_chained_direction);
}
}
}
--sharc_icount;
};
return cycles - sharc_icount;
}
unsigned dasmjag(int dsp_type, char * bufferOut, unsigned pc)
{
char buffer[64];
int op = ROPCODE(pc);
int reg1 = (op >> 5) & 31;
int reg2 = op & 31;
int size = 2;
pc += 2;
switch (op >> 10)
{
case 0: sprintf(buffer, "ADD R%02d,R%02d", reg1, reg2); break;
case 1: sprintf(buffer, "ADDC R%02d,R%02d", reg1, reg2); break;
case 2: sprintf(buffer, "ADDQ $%X,R%02d", convert_zero[reg1], reg2); break;
case 3: sprintf(buffer, "ADDQT $%X,R%02d", convert_zero[reg1], reg2); break;
case 4: sprintf(buffer, "SUB R%02d,R%02d", reg1, reg2); break;
case 5: sprintf(buffer, "SUBC R%02d,R%02d", reg1, reg2); break;
case 6: sprintf(buffer, "SUBQ $%X,R%02d", convert_zero[reg1], reg2); break;
case 7: sprintf(buffer, "SUBQT $%X,R%02d", convert_zero[reg1], reg2); break;
case 8: sprintf(buffer, "NEG R%02d", reg2); break;
case 9: sprintf(buffer, "AND R%02d,R%02d", reg1, reg2); break;
case 10: sprintf(buffer, "OR R%02d,R%02d", reg1, reg2); break;
case 11: sprintf(buffer, "XOR R%02d,R%02d", reg1, reg2); break;
case 12: sprintf(buffer, "NOT R%02d", reg2); break;
case 13: sprintf(buffer, "BTST $%X,R%02d", reg1, reg2); break;
case 14: sprintf(buffer, "BSET $%X,R%02d", reg1, reg2); break;
case 15: sprintf(buffer, "BCLR $%X,R%02d", reg1, reg2); break;
case 16: sprintf(buffer, "MULT R%02d,R%02d", reg1, reg2); break;
case 17: sprintf(buffer, "IMULT R%02d,R%02d", reg1, reg2); break;
case 18: sprintf(buffer, "IMULTN R%02d,R%02d", reg1, reg2); break;
case 19: sprintf(buffer, "RESMAC R%02d", reg2); break;
case 20: sprintf(buffer, "IMACN R%02d,R%02d", reg1, reg2); break;
case 21: sprintf(buffer, "DIV R%02d,R%02d", reg1, reg2); break;
case 22: sprintf(buffer, "ABS R%02d", reg2); break;
case 23: sprintf(buffer, "SH R%02d,R%02d", reg1, reg2); break;
case 24: sprintf(buffer, "SHLQ $%X,R%02d", 32 - reg1, reg2); break;
case 25: sprintf(buffer, "SHRQ $%X,R%02d", convert_zero[reg1], reg2); break;
case 26: sprintf(buffer, "SHA R%02d,R%02d", reg1, reg2); break;
case 27: sprintf(buffer, "SHARQ $%X,R%02d", convert_zero[reg1], reg2); break;
case 28: sprintf(buffer, "ROR R%02d,R%02d", reg1, reg2); break;
case 29: sprintf(buffer, "RORQ $%X,R%02d", convert_zero[reg1], reg2); break;
case 30: sprintf(buffer, "CMP R%02d,R%02d", reg1, reg2); break;
case 31: sprintf(buffer, "CMPQ %s,R%02d", signed_16bit((int16_t)(reg1 << 11) >> 11), reg2);break;
case 32: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, "SAT8 R%02d", reg2);
else
sprintf(buffer, "SUBQMOD $%X,R%02d", convert_zero[reg1], reg2);
break;
case 33: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, "SAT16 R%02d", reg2);
else
sprintf(buffer, "SAT16S R%02d", reg2);
break;
case 34: sprintf(buffer, "MOVE R%02d,R%02d", reg1, reg2); break;
case 35: sprintf(buffer, "MOVEQ %d,R%02d", reg1, reg2); break;
case 36: sprintf(buffer, "MOVETA R%02d,R%02d", reg1, reg2); break;
case 37: sprintf(buffer, "MOVEFA R%02d,R%02d", reg1, reg2); break;
case 38: sprintf(buffer, "MOVEI #$%X,R%02d", ROPCODE(pc) | (ROPCODE(pc+2)<<16), reg2); size = 6; break;
case 39: sprintf(buffer, "LOADB (R%02d),R%02d", reg1, reg2); break;
case 40: sprintf(buffer, "LOADW (R%02d),R%02d", reg1, reg2); break;
case 41: sprintf(buffer, "LOAD (R%02d),R%02d", reg1, reg2); break;
case 42: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, "LOADP (R%02d),R%02d", reg1, reg2);
else
sprintf(buffer, "SAT32S R%02d", reg2);
break;
case 43: sprintf(buffer, "LOAD (R14+$%X),R%02d", convert_zero[reg1]*4, reg2);break;
case 44: sprintf(buffer, "LOAD (R15+$%X),R%02d", convert_zero[reg1]*4, reg2);break;
case 45: sprintf(buffer, "STOREB R%02d,(R%02d)", reg2, reg1); break;
case 46: sprintf(buffer, "STOREW R%02d,(R%02d)", reg2, reg1); break;
case 47: sprintf(buffer, "STORE R%02d,(R%02d)", reg2, reg1); break;
case 48: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, "STOREP R%02d,(R%02d)", reg2, reg1);
else
sprintf(buffer, "MIRROR R%02d", reg2);
break;
case 49: sprintf(buffer, "STORE R%02d,(R14+$%X)", reg2, convert_zero[reg1]*4);break;
case 50: sprintf(buffer, "STORE R%02d,(R15+$%X)", reg2, convert_zero[reg1]*4);break;
case 51: sprintf(buffer, "MOVE PC,R%02d", reg2); break;
case 52: sprintf(buffer, "JUMP %s(R%02d)", condition[reg2], reg1); break;
case 53: sprintf(buffer, "JR %s$%X", condition[reg2], pc + ((int8_t)(reg1 << 3) >> 2)); break;
case 54: sprintf(buffer, "MMULT R%02d,R%02d", reg1, reg2); break;
case 55: sprintf(buffer, "MTOI R%02d,R%02d", reg1, reg2); break;
case 56: sprintf(buffer, "NORMI R%02d,R%02d", reg1, reg2); break;
case 57: sprintf(buffer, "NOP"); break;
case 58: sprintf(buffer, "LOAD (R14+R%02d),R%02d", reg1, reg2); break;
case 59: sprintf(buffer, "LOAD (R15+R%02d),R%02d", reg1, reg2); break;
case 60: sprintf(buffer, "STORE R%02d,(R14+R%02d)", reg2, reg1); break;
case 61: sprintf(buffer, "STORE R%02d,(R15+R%02d)", reg2, reg1); break;
case 62: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, "SAT24 R%02d", reg2);
else
sprintf(buffer, "illegal [%d,%d]", reg1, reg2);
break;
case 63: if (dsp_type == JAGUAR_GPU)
sprintf(buffer, (reg1 ? "UNPACK R%02d" : "PACK R%02d"), reg2);
else
sprintf(buffer, "ADDQMOD $%X,R%02d", convert_zero[reg1], reg2);
break;
}
if (size == 2)
sprintf(bufferOut, "%04X %-24s", op, buffer);
else
{
uint16_t word1 = ROPCODE(pc), word2 = ROPCODE(pc + 2);
sprintf(bufferOut, "%04X %04X %04X %-24s", op, word1, word2, buffer);
}
return size;
}
