/**
* Sets Analog Pin value in volts
* @param context SCPI context
* @return success or failure
*/
scpi_result_t RP_AnalogPinValue(scpi_t * context) {
int32_t choice;
double value;
/* Read first parameter - APIN */
if (!SCPI_ParamChoice(context, scpi_RpApin, &choice, true)) {
RP_LOG(LOG_ERR, "*ANALOG:PIN is missing first parameter.\n");
return SCPI_RES_ERR;
}
/* Read second parameter - VALUE */
if (!SCPI_ParamDouble(context, &value, true)) {
RP_LOG(LOG_ERR, "*ANALOG:PIN is missing second parameter.\n");
return SCPI_RES_ERR;
}
// Convert port into pin id
rp_apin_t pin = choice;
/* Set pin value */
int result = rp_ApinSetValue(pin, (float) value);
if (RP_OK != result){
RP_LOG(LOG_ERR, "*ANALOG:PIN Failed to set pin value: %s\n", rp_GetError(result));
return SCPI_RES_ERR;
}
RP_LOG(LOG_INFO, "*ANALOG:PIN Successfully set port value.\n");
return SCPI_RES_OK;
}
/**
* Returns Analog Pin value in volts to SCPI context
* @param context SCPI context
* @return success or failure
*/
scpi_result_t RP_AnalogPinValueQ(scpi_t * context) {
int32_t choice;
/* Read first parameter - APIN */
if (!SCPI_ParamChoice(context, scpi_RpApin, &choice, true)) {
RP_LOG(LOG_ERR, "*ANALOG:PIN? is missing first parameter.\n");
return SCPI_RES_ERR;
}
// Convert port into pin id
rp_apin_t pin = choice;
// Now get the pin value
float value;
int result = rp_ApinGetValue(pin, &value);
if (RP_OK != result){
RP_LOG(LOG_ERR, "*ANALOG:PIN? Failed to get pin value: %s\n", rp_GetError(result));
return SCPI_RES_ERR;
}
// Return back result
SCPI_ResultDouble(context, value);
RP_LOG(LOG_INFO, "*ANALOG:PIN? Successfully returned port value.\n");
return SCPI_RES_OK;
}
scpi_result_t RP_AnalogPinReset(scpi_t *context) {
int result = rp_ApinReset();
if (RP_OK != result) {
RP_LOG(LOG_ERR, "ANALOG:RST Failed to reset Red "
"Pitaya analog resources: %s\n" , rp_GetError(result));
return SCPI_RES_ERR;
}
RP_LOG(LOG_INFO, "*ANALOG:RST Successfully reset analog pin resources.\n");
return SCPI_RES_OK;
}
scpi_result_t RP_ReleaseAll(scpi_t *context){
int result = rp_Release();
if(result != RP_OK){
RP_LOG(LOG_ERR, "*RP:RELEASE Failed to release Red "
"Pitaya modules: %s\n", rp_GetError(result));
return SCPI_RES_ERR;
}
RP_LOG(LOG_INFO, "*RP:RELEASE Successfully released Red Pitaya modules.\n");
return SCPI_RES_OK;
}
scpi_result_t RP_InitAll(scpi_t *context){
int result = rp_Init();
if(result != RP_OK){
RP_LOG(LOG_ERR, "*RP:INIT Failed to initialize Red "
"Pitaya modules: %s\n", rp_GetError(result));
return SCPI_RES_ERR;
}
RP_LOG(LOG_INFO, "*RP:INIT Successfully inizitalized Red Pitaya modules.\n");
return SCPI_RES_OK;
}
scpi_result_t RP_EnableDigLoop(scpi_t *context){
int result = rp_EnableDigitalLoop(true);
if(result != RP_OK){
RP_LOG(LOG_ERR, "*RP:DIG:LOop Failed to initialize Red Pitaya"
" digital loop: %s\n", rp_GetError(result));
return SCPI_RES_ERR;
}
RP_LOG(LOG_INFO, "*RP:DIG:LOop Successfully initialize Red Pitaya"
" digital loop.\n");
return SCPI_RES_OK;
}
/* Parse channel */
int RP_ParseChArgv(scpi_t *context, rp_channel_t *channel){
int32_t ch_usr[1];
SCPI_CommandNumbers(context, ch_usr, 1, SCPI_CMD_NUM);
if(ch_usr[0] < MIN_CH || ch_usr[0] > MAX_CH){
RP_LOG(LOG_ERR, "ERROR: Invalid channel number: %.*s\n", 50, context->param_list.cmd_raw.data);
return RP_EOOR;
}
*channel = ch_usr[0] - 1;
return RP_OK;
}
scpi_result_t RP_FpgaBitStream(scpi_t *context){
const char *fpga_dir = "/opt/redpitaya/fpga/fpga_";
const char *param;
size_t param_len;
int fo, fi, fpga_s, fpga_dir_s;
struct stat st;
/* Read first param(fpga bit file typ (0.93, 0.94)) fom context */
if(!SCPI_ParamCharacters(context, ¶m, ¶m_len, true)){
RP_LOG(LOG_ERR, "*RP:FPGA:BITSTR Failed to parse first parameter.\n");
return SCPI_RES_ERR;
}
fpga_dir_s = strlen(fpga_dir) + param_len + strlen(".bit") + 2;
/* Get fpga image path */
char fpga_file[fpga_dir_s];
char delim_param[param_len];
strncpy(delim_param, param, param_len);
delim_param[param_len] = '\0';
snprintf(fpga_file, fpga_dir_s, "%s%s.bit", &fpga_dir[0], &delim_param[0]);
fpga_file[fpga_dir_s - 1] = '\0';
/* Load new fpga image into /dev/xdevcfg */
fo = open("/dev/xdevcfg", O_WRONLY);
if(fo < 0){
RP_LOG(LOG_ERR, "*RP:FPGA:BITstr Failed to open output file.\n");
return SCPI_RES_ERR;
}
fi = open(fpga_file, O_RDONLY);
if(fi < 0){
RP_LOG(LOG_ERR, "*RP:FPGA:BITstr Failed to open input file: %d\n", fi);
return SCPI_RES_ERR;
}
/* Get FPGA size */
stat(fpga_file, &st);
fpga_s = st.st_size;
char fi_buff[fpga_s];
/* Read FPGA file into fi_buff */
if(read(fi, &fi_buff, fpga_s) < 0){
RP_LOG(LOG_ERR, "*RP:FPGA:BITstr Unable to read "
"fpga bit stream into buffer: %d\n", fo);
return SCPI_RES_ERR;
}
if(write(fo, &fi_buff, fpga_s) < 0){
RP_LOG(LOG_ERR, "*RP:FPGA:BITstr Unable to write fpga "
"bit stream: %d\n", fo);
return SCPI_RES_ERR;
}
/* Close resources */
close(fi);
close(fo);
RP_LOG(LOG_INFO, "*RP:FPGA:BITstr Successfully loaded FPGA bit stream.\n");
return SCPI_RES_OK;
}
