static trx_retval_t trx_init(void)
{
tal_trx_status_t trx_status;
uint8_t poll_counter = 0;
/* Ensure control lines have correct levels. */
RST_HIGH();
SLP_TR_LOW();
/* Wait typical time. */
DELAY_US(P_ON_TO_CLKM_AVAILABLE_TYP_US);
/* Apply reset pulse */
RST_LOW();
DELAY_US(RST_PULSE_WIDTH_US);
RST_HIGH();
/* Verify that TRX_OFF can be written */
do {
/* Wait not more than max. value of TR1. */
if (poll_counter == P_ON_TO_CLKM_ATTEMPTS) {
return TRX_FAILURE;
}
/* Wait a short time interval. */
DELAY_US(TRX_POLL_WAIT_TIME_US);
poll_counter++;
/* Check if AT86RF212 is connected; omit manufacturer id check */
}
while (pal_trx_reg_read(RG_PART_NUM) != PART_NUM_AT86RF212);
/* Set trx to off mode */
pal_trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
/* Verify that the trx has reached TRX_OFF. */
poll_counter = 0;
do {
/* Wait a short time interval. */
DELAY_US(TRX_POLL_WAIT_TIME_US);
trx_status = (tal_trx_status_t) pal_trx_bit_read(SR_TRX_STATUS);
/* Wait not more than max attempts for state transition */
if (poll_counter == SLEEP_TO_TRX_OFF_ATTEMPTS) {
return TRX_FAILURE;
}
poll_counter++;
} while (trx_status != TRX_OFF);
tal_trx_status = TRX_OFF;
return TRX_SUCCESS;
}
static trx_retval_t trx_reset(void)
{
tal_trx_status_t trx_status;
uint8_t poll_counter = 0;
/* trx might sleep, so wake it up */
SLP_TR_LOW();
DELAY_US(SLEEP_TO_TRX_OFF_TYP_US);
/* Apply reset pulse */
RST_LOW();
DELAY_US(RST_PULSE_WIDTH_US);
RST_HIGH();
/* verify that trx has reached TRX_OFF */
do {
/* Wait a short time interval. */
DELAY_US(TRX_POLL_WAIT_TIME_US);
trx_status = (tal_trx_status_t) pal_trx_bit_read(SR_TRX_STATUS);
/* Wait not more than max. */
if (poll_counter == SLEEP_TO_TRX_OFF_ATTEMPTS) {
return TRX_FAILURE;
}
poll_counter++;
} while (trx_status != TRX_OFF);
tal_trx_status = TRX_OFF;
return TRX_SUCCESS;
}
void initM64()
{
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock
RST_HIGH() ; /* RST high */
configure_pins( GPIO_Pin_M64_RST, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTC ) ;
USART1_Configure( 200000 ) ;
}
void finit3310( void )
{
CS_HIGH();
RST_HIGH();
DC_HIGH();
delay3310( 100000 );
}
void ispDisconnect()
{
/* set all ISP pins inputs */
RST_HIGH() ; /* RST high */
// configure_pins( GPIO_Pin_M64_RST, PIN_INPUT | PIN_PORTC ) ;
configure_pins( GPIO_Pin_M64_SCK, PIN_INPUT | PIN_PORTA ) ;
configure_pins( GPIO_Pin_M64_MOSI, PIN_INPUT | PIN_PORTB ) ;
}
void init3310( void )
{
palSetPad( PORT_CS, PAD_CS ); // Set CS high
palSetPadMode( PORT_SCK, PAD_SCK, PAL_MODE_STM32_ALTERNATE_PUSHPULL ); // SCK
palSetPadMode( PORT_MOSI, PAD_MOSI, PAL_MODE_STM32_ALTERNATE_PUSHPULL ); // MISO
palSetPadMode( PORT_CS, PAD_CS, PAL_MODE_OUTPUT_PUSHPULL ); // CS
CS_HIGH();
DC_HIGH();
RST_HIGH();
palSetPadMode( PORT_DC, PAD_DC, PAL_MODE_OUTPUT_PUSHPULL );
palSetPadMode( PORT_CS, PAD_CS, PAL_MODE_OUTPUT_PUSHPULL );
palSetPadMode( PORT_RST, PAD_RST, PAL_MODE_OUTPUT_PUSHPULL );
delay3310( 100000 );
}
void ispConnect()
{
init_hw_timer() ;
/* all ISP pins are inputs before */
/* now set output pins */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ; // Enable portB clock
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock
configure_pins( GPIO_Pin_M64_RST, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTC ) ;
configure_pins( GPIO_Pin_M64_SCK, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTA ) ;
configure_pins( GPIO_Pin_M64_MOSI, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTB ) ;
/* reset device */
RST_LOW() ; /* RST low */
SCK_LOW() ; /* SCK low */
/* positive reset pulse > 2 SCK (target) */
ispDelay();
RST_HIGH() ; /* RST high */
clockWait(64) ;
RST_LOW() ; /* RST low */
}
void ispForceResetOff()
{
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ; // Enable portC clock
configure_pins( GPIO_Pin_M64_RST, PIN_OUTPUT | PIN_PUSHPULL | PIN_OS25 | PIN_PORTC ) ;
RST_HIGH() ; /* RST high */
}
void rstHigh(void)
{
RST_HIGH();
}
/**
* @brief Resets transceiver(s)
*
* @param trx_id Transceiver identifier
*
* @return MAC_SUCCESS if the transceiver returns TRX_OFF
* FAILURE otherwise
*/
retval_t trx_reset(trx_id_t trx_id)
{
ENTER_TRX_REGION();
uint32_t start_time;
uint32_t current_time;
pal_get_current_time(&start_time);
if (trx_id == RFBOTH) {
TAL_RF_IRQ_CLR_ALL(RF09);
TAL_RF_IRQ_CLR_ALL(RF24);
tal_state[RF09] = TAL_RESET;
tal_state[RF24] = TAL_RESET;
/* Apply reset pulse; low active */
#ifdef IQ_RADIO
RST_LOW();
PAL_WAIT_1_US();
PAL_WAIT_1_US();
RST_HIGH();
#if (BOARD_TYPE == EVAL215_FPGA)
pal_timer_delay(10000);
#endif
RST_LOW();
PAL_WAIT_1_US();
RST_HIGH();
#else
RST_LOW();
PAL_WAIT_1_US();
RST_HIGH();
#endif
/* Wait for IRQ line */
while (1) {
/*
* @ToDo: Use a different macro for IRQ line; the
*polarity might be
* different after reset
*/
#ifdef IQ_RADIO
if ((PAL_DEV_IRQ_GET(RF215_BB) == HIGH) &&
(PAL_DEV_IRQ_GET(RF215_RF) == HIGH)) {
break;
}
#else
if (TRX_IRQ_GET() == HIGH) {
break;
}
#endif
/* Handle timeout */
pal_get_current_time(¤t_time);
/* @ToDo: Remove magic number */
if (pal_sub_time_us(current_time, start_time) > 1000) {
return FAILURE;
}
}
#ifdef IQ_RADIO
trx_state[RF09] = (rf_cmd_state_t)pal_dev_reg_read(RF215_RF,
RG_RF09_STATE);
trx_state[RF24] = (rf_cmd_state_t)pal_dev_reg_read(RF215_RF,
RG_RF24_STATE);
rf_cmd_state_t bb_trx_state[NUM_TRX];
bb_trx_state[RF09] = (rf_cmd_state_t)pal_dev_reg_read(RF215_BB,
RG_RF09_STATE);
bb_trx_state[RF24] = (rf_cmd_state_t)pal_dev_reg_read(RF215_BB,
RG_RF24_STATE);
if ((bb_trx_state[RF09] != RF_TRXOFF) ||
(bb_trx_state[RF24] != RF_TRXOFF)) {
return FAILURE;
}
#else
trx_state[RF09] = trx_reg_read(RG_RF09_STATE);
trx_state[RF24] = trx_reg_read(RG_RF24_STATE);
#endif
if ((trx_state[RF09] != RF_TRXOFF) ||
(trx_state[RF24] != RF_TRXOFF)) {
return FAILURE;
}
/* Get all IRQ status information */
#ifdef IQ_RADIO
bb_irq_handler_cb();
rf_irq_handler_cb();
#else
trx_irq_handler_cb();
#endif
TAL_RF_IRQ_CLR(RF09, RF_IRQ_WAKEUP);
TAL_RF_IRQ_CLR(RF24, RF_IRQ_WAKEUP);
} else {
TAL_RF_IRQ_CLR_ALL(trx_id);
tal_state[trx_id] = TAL_RESET;
/* Trigger reset of device */
uint16_t reg_offset = RF_BASE_ADDR_OFFSET * trx_id;
#ifdef IQ_RADIO
pal_trx_reg_write(RF215_RF, reg_offset + RG_RF09_CMD, RF_RESET);
pal_trx_reg_write(RF215_BB, reg_offset + RG_RF09_CMD, RF_RESET);
#else
trx_reg_write(reg_offset + RG_RF09_CMD, RF_RESET);
#endif
/* Wait for IRQ line */
while (1) {
#ifdef IQ_RADIO
if ((PAL_DEV_IRQ_GET(RF215_BB) == HIGH) &&
(PAL_DEV_IRQ_GET(RF215_RF) == HIGH)) {
break;
}
#else
if (TRX_IRQ_GET() == HIGH) {
break;
}
#endif
/* Handle timeout */
pal_get_current_time(¤t_time);
/* @ToDo: Remove magic number */
if (pal_sub_time_us(current_time, start_time) > 1000) {
return FAILURE;
}
}
trx_state[trx_id] = RF_TRXOFF;
/* Get all IRQ status information */
#ifdef IQ_RADIO
bb_irq_handler_cb();
rf_irq_handler_cb();
#else
trx_irq_handler_cb();
#endif
TAL_RF_IRQ_CLR(trx_id, RF_IRQ_WAKEUP);
}
#ifdef IQ_RADIO
pal_trx_irq_flag_clr(RF215_BB);
pal_trx_irq_flag_clr(RF215_RF);
#else
pal_trx_irq_flag_clr();
#endif
LEAVE_TRX_REGION();
return MAC_SUCCESS;
}