INT rtv_InitSystem(void)
{
int i;
U8 read0, read1;
g_bRtvIntrMaskReg = 0xFF;
#if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
#ifdef RTV_IF_SPI
#define WR27_VAL 0x10
#else
#define WR27_VAL 0x12
#endif
#define WR29_VAL 0x31
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x29, WR29_VAL); /* BUFSEL first! */
RTV_REG_SET(0x27, WR27_VAL);
read0 = RTV_REG_GET(0x27);
read1 = RTV_REG_GET(0x29);
RTV_DBGMSG2("read0(0x%02X), read1(0x%02X)\n", read0, read1);
if ((read0 == WR27_VAL) && (read1 == WR29_VAL))
goto RTV_POWER_ON_SUCCESS;
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#else
RTV_REG_MAP_SEL(HOST_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x05, 0x00);
RTV_REG_SET(0x08, 0x10);
read0 = RTV_REG_GET(0x05);
read1 = RTV_REG_GET(0x08);
RTV_DBGMSG2("read0(0x%02X), read1(0x%02X)\n", read0, read1);
if ((read0 == 0x00) && (read1 == 0x10))
goto RTV_POWER_ON_SUCCESS;
RTV_REG_SET(0x07, 0x00);
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#endif
RTV_DBGMSG1("rtv_InitSystem: Power On Check error: %d\n", i);
return RTV_POWER_ON_CHECK_ERROR;
RTV_POWER_ON_SUCCESS:
return RTV_SUCCESS;
}
static int rtv_InitBoot(void)
{
int i;
U8 read0, read1;
#if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
#ifdef RTV_IF_SPI
#define WR27_VAL 0x11
#else
#define WR27_VAL 0x13
#endif
#define WR29_VAL 0x31
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x29, WR29_VAL); /* BUFSEL first! */
RTV_REG_SET(0x27, WR27_VAL);
read0 = RTV_REG_GET(0x27);
read1 = RTV_REG_GET(0x29);
RTV_DBGMSG2("[rtv_InitBoot] read27(0x%02X), read29(0x%02X)\n",
read0, read1);
if ((read0 == WR27_VAL) && (read1 == WR29_VAL))
return RTV_SUCCESS;
RTV_DBGMSG1("[rtv_InitBoot] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#else
RTV_REG_MAP_SEL(HOST_PAGE);
for (i = 0; i < 100; i++) {
read0 = RTV_REG_GET(0x00);
read1 = RTV_REG_GET(0x01);
RTV_DBGMSG2("[rtv_InitBoot] read27(0x%02X), read29(0x%02X)\n",
read0, read1);
if ((read0 == 0xC6) && (read1 == 0x43))
return RTV_SUCCESS;
RTV_DBGMSG1("[rtv_InitBoot] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#endif
RTV_DBGMSG1("[rtv_InitBoot] Power On Check error: %d\n", i);
return RTV_POWER_ON_CHECK_ERROR;
}
void rtv_ConfigureHostIF(void)
{
#if defined(RTV_IF_MPEG2_SERIAL_TSIF) || defined(RTV_IF_QUALCOMM_TSIF) || defined(RTV_IF_MPEG2_PARALLEL_TSIF) || defined(RTV_IF_SPI_SLAVE)
RTV_REG_MAP_SEL(HOST_PAGE);
RTV_REG_SET(0x77, 0x15); // TSIF Enable
RTV_REG_SET(0x22, 0x48);
#if defined(RTV_IF_MPEG2_PARALLEL_TSIF)
RTV_REG_SET(0x04, 0x01); // I2C + TSIF Mode Enable
#else
RTV_REG_SET(0x04, 0x29); // I2C + TSIF Mode Enable
#endif
RTV_REG_SET(0x0C, 0xF4); // TSIF Enable
#elif defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
RTV_REG_MAP_SEL(HOST_PAGE);
RTV_REG_SET(0x77, 0x14); //SPI Mode Enable
RTV_REG_SET(0x04, 0x28); // SPI Mode Enable
RTV_REG_SET(0x0C, 0xF5);
#else
#error "Code not present"
#endif
}
void rtvOEM_ConfigureInterrupt(void)
{
#if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
RTV_REG_SET(0x21, SPI_INTR_POL_ACTIVE|0x02);
#ifdef RTV_IF_SPI
RTV_REG_SET(0x27, 0x01); /* AUTO_INTR: 0, Recovery mode ON */
#endif
RTV_REG_SET(0x2B, RTV_SPI_INTR_DEACT_PRD_VAL);
RTV_REG_SET(0x2A, 1); /* SRAM init */
RTV_REG_SET(0x2A, 0);
#endif
}
/*====================================================================
FUNCTION mtv350_use_FM_path(Reg. 0x27)
DESCRIPTION earjack : FM path set 0x92, retractable : set 0x96, don't need antenna switch.
DEPENDENCIES
RETURN VALUE
SIDE EFFECTS
======================================================================*/
void mtv350_use_FM_path(int set_FM_path)
{
RTV_REG_MAP_SEL(RF_PAGE);
RTV_REG_SET(0x27, (0x92 | (set_FM_path<<2)));
TDMB_MSG_RTV_BB("Ant type[%d] : RTV use FM path set[%x]\n ",set_FM_path, (0x92 | (set_FM_path<<2)));
}
static void mtv319_pull_data(void)
{
U8 ifreg, istatus;
RTV_GUARD_LOCK;
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
ifreg = RTV_REG_GET(0x55);
if (ifreg != 0xAA) {
mtv319_spi_recover(stream_buff, MTV319_INTERRUPT_SIZE);
DPRINTK("Interface error 1\n");
}
istatus = RTV_REG_GET(0x10);
if (istatus & (U8)(~SPI_INTR_BITS)) {
mtv319_spi_recover(stream_buff, MTV319_INTERRUPT_SIZE);
DPRINTK("Interface error 2 (0x%02X)\n", istatus);
goto exit_read_mem;
}
if (istatus & SPI_UNDERFLOW_INTR) {
RTV_REG_SET(0x2A, 1);
RTV_REG_SET(0x2A, 0);
DPRINTK("UDF: 0x%02X\n", istatus);
goto exit_read_mem;
}
if (istatus & SPI_THRESHOLD_INTR) {
RTV_REG_MAP_SEL(SPI_MEM_PAGE);
RTV_REG_BURST_GET(0x10, stream_buff, MTV319_INTERRUPT_SIZE);
tdmb_store_data(stream_buff, MTV319_INTERRUPT_SIZE);
if (istatus & SPI_OVERFLOW_INTR)
DPRINTK("OVF: 0x%02X\n", istatus); /* To debug */
} else
DPRINTK("No data interrupt (0x%02X)\n", istatus);
exit_read_mem:
RTV_GUARD_FREE;
}
static void mtv318_pull_data(void)
{
unsigned char int_type_val1;
unsigned char int_type_val2;
RTV_GUARD_LOCK;
RTV_REG_MAP_SEL(DD_PAGE);
int_type_val1 = RTV_REG_GET(INT_E_STATL);
int_type_val2 = RTV_REG_GET(INT_E_STATH);
/*===========================================
* Processing MSC1 interrupt.
* T-DMB/DAB: 1 VIDEO data or 1 AUDIO data
* 1 seg: 1 VIDEO data
* FM: PCM data
*===========================================*/
/* MSC1 memory overflow or under run */
if (int_type_val1&(MSC1_E_INT|MSC1_E_OVER_FLOW|MSC1_E_UNDER_FLOW)) {
if (int_type_val1 & (MSC1_E_OVER_FLOW|MSC1_E_UNDER_FLOW)) {
rtv_ClearAndSetupMemory_MSC1();
/* MSC1 Interrupt status clear */
RTV_REG_SET(INT_E_UCLRL, 0x04);
} else {
/* Get the frame data using CPU or DMA.
RTV_REG_BURST_GET() macro should implemented by user. */
RTV_REG_MAP_SEL(MSC1_PAGE);
RTV_REG_BURST_GET(0x10, stream_buff,
MTV318_INTERRUPT_SIZE+1);
RTV_REG_MAP_SEL(DD_PAGE);
/* MSC1 Interrupt status clear */
RTV_REG_SET(INT_E_UCLRL, 0x04);
tdmb_store_data(&stream_buff[1], MTV318_INTERRUPT_SIZE);
}
}
RTV_GUARD_FREE;
}
INT rtv_InitSystem(E_RTV_TV_MODE_TYPE eTvMode, E_RTV_ADC_CLK_FREQ_TYPE eAdcClkFreqType)
{
INT nRet;
int i;
g_afRtvChannelChange[RaonTvChipIdx] = FALSE;
g_afRtvStreamEnabled[RaonTvChipIdx] = FALSE;
#if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
g_abRtvIntrMaskRegL[RaonTvChipIdx] = 0xFF;
#else
#if defined(RTV_TDMB_ENABLE) && !defined(RTV_TDMB_MULTI_SUB_CHANNEL_ENABLE) /* Single sub channel mode */
g_abRtvIntrMaskRegL[RaonTvChipIdx] = 0xFF;
#endif
#endif
/* In case of SPI interface or FIC interrupt mode for T-DMB, we should lock the register page. */
RTV_GUARD_INIT;
for(i=0; i<100; i++)
{
//RTV_DBGMSG0("[rtv_InitSystem] 1\n");
RTV_REG_MAP_SEL(HOST_PAGE);
//RTV_DBGMSG0("[rtv_InitSystem] 2\n");
RTV_REG_SET(0x7D, 0x06);
if(RTV_REG_GET(0x7D) == 0x06)
{
goto RTV_POWER_ON_SUCCESS;
}
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
RTV_DBGMSG1("rtv_InitSystem: Power On Check error: %d\n", i);
return RTV_POWER_ON_CHECK_ERROR;
RTV_POWER_ON_SUCCESS:
rtvRF_ConfigurePowerType(eTvMode);
if((nRet=rtvRF_ConfigureAdcClock(eTvMode, eAdcClkFreqType)) != RTV_SUCCESS)
return nRet;
return RTV_SUCCESS;
}
INT rtv_InitSystem(E_RTV_TV_MODE_TYPE eTvMode,
E_RTV_ADC_CLK_FREQ_TYPE eAdcClkFreqType)
{
INT nRet;
int i;
U8 read0, read1;
g_fRtvChannelChange = FALSE;
g_fRtvStreamEnabled = FALSE;
g_bRtvIntrMaskRegL = 0xFF;
#if defined(RTV_IF_SPI) || defined(RTV_IF_EBI2)
#ifdef RTV_IF_SPI
#define WR27_VAL 0x11
#else
#define WR27_VAL 0x13
#endif
#define WR29_VAL 0x31
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x29, WR29_VAL); /* BUFSEL first! */
RTV_REG_SET(0x27, WR27_VAL);
read0 = RTV_REG_GET(0x27);
read1 = RTV_REG_GET(0x29);
RTV_DBGMSG2("read27(0x%02X), read29(0x%02X)\n", read0, read1);
if ((read0 == WR27_VAL) && (read1 == WR29_VAL))
goto RTV_POWER_ON_SUCCESS;
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#else
RTV_REG_MAP_SEL(HOST_PAGE);
for (i = 0; i < 100; i++) {
read0 = RTV_REG_GET(0x00);
read1 = RTV_REG_GET(0x01);
RTV_DBGMSG2("read27(0x%02X), read29(0x%02X)\n", read0, read1);
if ((read0 == 0xC6) && (read1 == 0x43))
goto RTV_POWER_ON_SUCCESS;
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#endif
RTV_DBGMSG1("rtv_InitSystem: Power On Check error: %d\n", i);
return RTV_POWER_ON_CHECK_ERROR;
RTV_POWER_ON_SUCCESS:
rtvRF_ConfigurePowerType(eTvMode);
nRet = rtvRF_ChangeAdcClock(eTvMode, eAdcClkFreqType, 500);
if (nRet != RTV_SUCCESS)
return nRet;
return RTV_SUCCESS;
}
INT rtv_InitSystem(void)
{
int i;
U8 read0, read1;
U8 rev_num;
U8 ALDO_OUT = 0, DLDO_OUT = 0;
#ifdef RTV_DUAL_DIVERISTY_ENABLE
U8 S_ALDO_OUT = 0, S_DLDO_OUT = 0;
#endif
g_bRtvIntrMaskReg = 0x3F;
#if defined(RTV_IF_SPI) || defined(RTV_IF_SPI_TSIFx) || defined(RTV_IF_EBI2)
#define WR27_VAL (0x50|SPI_INTR_POL_ACTIVE)
#define WR29_VAL 0x10
for (i = 0; i < 100; i++) {
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
RTV_REG_SET(0x29, WR29_VAL); /* BUFSEL first! */
RTV_REG_SET(0x27, WR27_VAL);
read0 = RTV_REG_GET(0x27);
read1 = RTV_REG_GET(0x29);
#if defined(RTV_SPI_HIGH_SPEED_ENABLE)
RTV_REG_MAP_SEL(RF_PAGE);
#if (RTV_SRC_CLK_FREQ_KHz == 19200)
RTV_REG_SET(0xB6, 0x04);
RTV_REG_SET(0xB6, 0x24); /* DIV8 */
#else
RTV_REG_SET(0xB6, 0x05);
RTV_REG_SET(0xB6, 0x25); /* DIV8 */
#endif
#endif
RTV_REG_MAP_SEL(TOP_PAGE);
RTV_REG_SET(0x0C, 0xC3);
RTV_DBGMSG2("read0(0x%02X), read1(0x%02X)\n", read0, read1);
if ((read0 == WR27_VAL) && (read1 == WR29_VAL)) {
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
RTV_REG_SET(0x21, 0x87);
RTV_REG_SET(0x22, 0x00);
goto RTV_POWER_ON_SUCCESS;
}
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#else
RTV_REG_MAP_SEL(TOP_PAGE);
RTV_REG_SET(0x0C, 0xC3);
for (i = 0; i < 100; i++) {
read0 = RTV_REG_GET(0x00);
read1 = RTV_REG_GET(0x01);
RTV_DBGMSG2("read0(0x%02X), read1(0x%02X)\n", read0, read1);
if ((read0 == 0xC6))
goto RTV_POWER_ON_SUCCESS;
RTV_DBGMSG1("[rtv_InitSystem] Power On wait: %d\n", i);
RTV_DELAY_MS(5);
}
#endif
RTV_DBGMSG1("rtv_InitSystem: Power On Check error: %d\n", i);
return RTV_POWER_ON_CHECK_ERROR;
RTV_POWER_ON_SUCCESS:
#if 1
RTV_REG_MAP_SEL(RF_PAGE);
rev_num = (RTV_REG_GET(0x10) & 0xF0) >> 4 ;
#ifdef CHECK_REV_NUM
RTV_DBGMSG1("[rtv_InitSystem] REV number (%d)\n", rev_num);
#endif
if (rev_num >= 0x04) {
RTV_REG_MASK_SET(0x3B, 0x01, 0x01);
RTV_REG_MASK_SET(0x32, 0x01, 0x01);
}
#endif
#ifdef INTERFACE_TEST
#if defined(RTV_IF_SPI) || defined(RTV_IF_SPI_TSIFx) || defined(RTV_IF_EBI2)
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x22, 0x55);
read0 = RTV_REG_GET(0x22);
RTV_REG_SET(0x22, 0xAA);
read1 = RTV_REG_GET(0x22);
RTV_DBGMSG2("Before Power Setup :readSPI22_55(0x%02X), readSPI22_AA(0x%02X)\n",
read0, read1);
}
RTV_REG_MAP_SEL(RF_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x20, 0x55);
read0 = RTV_REG_GET(0x20);
RTV_REG_SET(0x20, 0xAA);
read1 = RTV_REG_GET(0x20);
RTV_DBGMSG2("Before Power Setup :readRF20_55(0x%02X), readRF20_AA(0x%02X)\n",
read0, read1);
}
#else
RTV_REG_MAP_SEL(RF_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x20, 0x55);
read0 = RTV_REG_GET(0x20);
RTV_REG_SET(0x20, 0xAA);
read1 = RTV_REG_GET(0x20);
RTV_DBGMSG2("Before Power Setup :readRF20_55(0x%02X), readRF20_AA(0x%02X)\n",
read0, read1);
}
#endif
#endif /* INTERFACE_TEST */
ALDO_OUT = 6;
DLDO_OUT = 1;
#ifdef RTV_DUAL_DIVERISTY_ENABLE
S_ALDO_OUT = 6;
S_DLDO_OUT = 1;
#endif
RTV_REG_MAP_SEL(RF_PAGE);
#ifdef RTV_DUAL_DIVERISTY_ENABLE
if (rtvMTV23x_Get_Diversity_Current_path() == DIVERSITY_MASTER) {
#endif
RTV_REG_MASK_SET(0xC8, 0x80, ((ALDO_OUT & 0x04) << 5));
RTV_REG_MASK_SET(0xD1, 0x80, ((ALDO_OUT & 0x02) << 6));
RTV_REG_MASK_SET(0xD2, 0x80, ((ALDO_OUT & 0x01) << 7));
RTV_REG_MASK_SET(0xD3, 0x80, ((DLDO_OUT & 0x04) << 5));
RTV_REG_MASK_SET(0xD5, 0x80, ((DLDO_OUT & 0x02) << 6));
RTV_REG_MASK_SET(0xD6, 0x80, ((DLDO_OUT & 0x01) << 7));
#ifdef RTV_DUAL_DIVERISTY_ENABLE
} else {
RTV_REG_MASK_SET(0xC8, 0x80, ((S_ALDO_OUT & 0x04) << 5));
RTV_REG_MASK_SET(0xD1, 0x80, ((S_ALDO_OUT & 0x02) << 6));
RTV_REG_MASK_SET(0xD2, 0x80, ((S_ALDO_OUT & 0x01) << 7));
RTV_REG_MASK_SET(0xD3, 0x80, ((S_DLDO_OUT & 0x04) << 5));
RTV_REG_MASK_SET(0xD5, 0x80, ((S_DLDO_OUT & 0x02) << 6));
RTV_REG_MASK_SET(0xD6, 0x80, ((S_DLDO_OUT & 0x01) << 7));
}
#endif
RTV_DELAY_MS(10);
RTV_REG_MASK_SET(0xC9, 0x80, 0x80);
#if defined(RTV_EXT_POWER_MODE)
RTV_REG_SET(0xCD, 0xCF);
#ifdef RTV_DUAL_DIVERISTY_ENABLE
RTV_REG_SET(0xCE, 0x35);
#else
RTV_REG_SET(0xCE, 0xB5);
#endif
#else /* Internal LDO Mode */
RTV_REG_SET(0xCD, 0x4F);
RTV_REG_SET(0xCE, 0x35);
#endif
#ifdef INTERFACE_TEST
#if defined(RTV_IF_SPI) || defined(RTV_IF_SPI_TSIFx) || defined(RTV_IF_EBI2)
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x22, 0x55);
read0 = RTV_REG_GET(0x22);
RTV_REG_SET(0x22, 0xAA);
read1 = RTV_REG_GET(0x22);
RTV_DBGMSG2("After Power Setup :readSPI22_55(0x%02X), readSPI22_AA(0x%02X)\n",
read0, read1);
}
RTV_REG_MAP_SEL(RF_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x20, 0x55);
read0 = RTV_REG_GET(0x20);
RTV_REG_SET(0x20, 0xAA);
read1 = RTV_REG_GET(0x20);
RTV_DBGMSG2("After Power Setup :readRF20_55(0x%02X), readRF20_AA(0x%02X)\n",
read0, read1);
}
#else
RTV_REG_MAP_SEL(RF_PAGE);
for (i = 0; i < 100; i++) {
RTV_REG_SET(0x20, 0x55);
read0 = RTV_REG_GET(0x20);
RTV_REG_SET(0x20, 0xAA);
read1 = RTV_REG_GET(0x20);
RTV_DBGMSG2("After Power Setup :readRF20_55(0x%02X), readRF20_AA(0x%02X)\n",
read0, read1);
}
#endif
#endif /* INTERFACE_TEST */
return RTV_SUCCESS;
}
/*-------------------------------------------------------------------------------------
int8 tunerbb_drv_mtv319_read_data(uint8* buffer, uint32* buffer_size)
(1) Reading MSC or MSC + FIC etc Data.
This function is used in EBI2 HOST Interface
(2) Return Value
Sucess : 1
Fail : 0 or negative interger (If there is error code)
(3) Argument
uint8* buffer (IN/OUT)
- buffer for Data
uint32* buffer_size (IN /OUT)
- Data Size
<notice> This function is used in only EBI2 HOST Interface
--------------------------------------------------------------------------------------- */
int8 tunerbb_drv_mtv319_read_data(uint8* buffer, uint32* buffer_size)
{
#if defined(STREAM_SLAVE_PARALLEL_UPLOAD) || defined(STREAM_SPI_UPLOAD)
#if defined(SPI_INTERFACE_CHECK)
uint8 ifreg, ifreg2;
UINT i;
#endif
uint8 istatus;
UINT intr_size, num_read_ts_chunk, tsp_read_len = 0;
TDMB_BB_HEADER_TYPE *dmb_header = (TDMB_BB_HEADER_TYPE *)buffer;
uint8 *tspb_ptr = (uint8 *)(buffer + sizeof(TDMB_BB_HEADER_TYPE));
uint8 intr_cnt;
#define MAX_NUM_READ_THRESHOLD_INTR 4
*buffer_size = 0; /* Init */
RTV_GUARD_LOCK;
intr_size = rtvTDMB_GetInterruptLevelSize();
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
#if defined(SPI_INTERFACE_CHECK)
for (i = 0; i < 10; i++)
{
ifreg = RTV_REG_GET(0x55);
ifreg2 = RTV_REG_GET(0x56);
if ((ifreg == 0xAA) && (ifreg2 == 0xAA))
break;
else
{
mtv319_spi_recover(buffer, MTV319_SPI_CMD_SIZE + intr_size);
DMBMSG("(%u) Interface error 1\n", i);
}
}
#endif
istatus = RTV_REG_GET(0x10);
if (istatus & (U8)(~SPI_INTR_BITS)) {
mtv319_spi_recover(buffer, MTV319_SPI_CMD_SIZE + intr_size);
RTV_REG_SET(0x2A, 1);
RTV_REG_SET(0x2A, 0);
DMBMSG("Interface error 2 (0x%02X)\n", istatus);
goto exit_read_mem;
}
if (istatus & SPI_UNDERFLOW_INTR)
{
RTV_REG_SET(0x2A, 1);
RTV_REG_SET(0x2A, 0);
DMBMSG("UDF: 0x%02X\n", istatus);
goto exit_read_mem;
}
if (istatus & SPI_THRESHOLD_INTR)
{
#if 0
if (!(istatus & SPI_OVERFLOW_INTR))
num_read_ts_chunk = 1;
else
num_read_ts_chunk = MAX_NUM_READ_THRESHOLD_INTR; /* Overflow */
#else
num_read_ts_chunk = 1;
#endif
//DMBMSG("num_read_ts_chunk (%u)\n", num_read_ts_chunk);
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
intr_cnt = RTV_REG_GET(0x12);
if (intr_cnt > 1)
DMBMSG("1 more threshold interrupt(%d)\n", intr_cnt);
RTV_REG_MAP_SEL(SPI_MEM_PAGE);
do {
RTV_REG_BURST_GET(0x10, tspb_ptr, intr_size);
//print_tsp(tspb_ptr, intr_size); /* To debug */
tspb_ptr += intr_size;
tsp_read_len += intr_size;
} while (--num_read_ts_chunk);
if (istatus & SPI_OVERFLOW_INTR)
DMBMSG("OVF: 0x%02X\n", istatus); /* To debug */
dmb_header->size = tsp_read_len;
dmb_header->data_type = opened_subch_info[0].data_type;
*buffer_size = sizeof(TDMB_BB_HEADER_TYPE) + tsp_read_len;
}
else
{
RTV_REG_MAP_SEL(SPI_CTRL_PAGE);
mtv319_spi_recover(buffer, MTV319_SPI_CMD_SIZE + intr_size);
RTV_REG_SET(0x2A, 1);
RTV_REG_SET(0x2A, 0);
DMBMSG("No data interrupt (0x%02X)\n", istatus);
}
exit_read_mem:
RTV_GUARD_FREE;
return MTV319_RESULT_SUCCESS;
#elif defined(STREAM_TS_UPLOAD)
return MTV319_RESULT_ERROR;
#endif
}
static int mtv250_ioctl(struct inode *inode, struct file *filp,
unsigned int cmd, unsigned long arg)
#endif
{
int ret = 0;
void __user *argp = (void __user *)arg;
RTV_IOCTL_REGISTER_ACCESS ioctl_register_access;
RTV_IOCTL_TEST_GPIO_INFO gpio_info;
U8 reg_page = 0;
UINT lock_mask;
UINT isdbt_ch_num;
RTV_ISDBT_TMCC_INFO isdbt_tmcc_info;
IOCTL_ISDBT_SIGNAL_INFO isdbt_signal_info;
IOCTL_ISDBT_LGE_TUNER_INFO lge_tuner_info;
switch( cmd )
{
case IOCTL_ISDBT_POWER_ON: // with adc clk type
mtv250_cb_ptr->tv_mode = DMB_TV_MODE_1SEG;
mtv250_cb_ptr->country_band_type = RTV_COUNTRY_BAND_JAPAN;
DMBMSG("[mtv] IOCTL_ISDBT_POWER_ON: country_band_type(%d)\n", mtv250_cb_ptr->country_band_type);
ret = mtv250_power_on();
if(ret != 0)
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_POWER_OFF:
DMBMSG("[mtv] IOCTL_ISDBT_POWER_OFF\n");
mtv250_power_off();
break;
case IOCTL_ISDBT_SCAN_FREQ:
if (copy_from_user(&isdbt_ch_num, argp, sizeof(UINT)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
ret = rtvISDBT_ScanFrequency(isdbt_ch_num);
// DMBMSG("[mtv] ISDBT SCAN(%d) result: %d\n", isdbt_ch_num, ret);
if(ret != RTV_SUCCESS)
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_SET_FREQ:
if (copy_from_user(&isdbt_ch_num, argp, sizeof(UINT)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
// DMBMSG("[mtv] IOCTL_ISDBT_SET_FREQ: %d\n", isdbt_ch_num);
ret=rtvISDBT_SetFrequency(isdbt_ch_num);
if(ret != RTV_SUCCESS)
{
DMBERR("[mtv] IOCTL_ISDBT_SET_FREQ error %d\n", ret);
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_GET_LOCK_STATUS:
// DMBMSG("[mtv] IOCTL_ISDBT_GET_LOCK_STATUS\n");
lock_mask=rtvISDBT_GetLockStatus();
if (copy_to_user(argp,&lock_mask, sizeof(UINT)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_GET_TMCC:
// DMBMSG("[mtv] IOCTL_ISDBT_GET_TMCC\n");
rtvISDBT_GetTMCC(&isdbt_tmcc_info);
if (copy_to_user(argp,&isdbt_tmcc_info, sizeof(RTV_ISDBT_TMCC_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_GET_SIGNAL_INFO:
// DMBMSG("[mtv] IOCTL_ISDBT_GET_SIGNAL_INFO\n");
isdbt_signal_info.ber = rtvISDBT_GetBER();
if(isdbt_signal_info.ber > 1500)
isdbt_signal_info.ber = 100000;
isdbt_signal_info.cnr = rtvISDBT_GetCNR() / RTV_ISDBT_CNR_DIVIDER;
isdbt_signal_info.cnr = 10 * isdbt_signal_info.cnr;
isdbt_signal_info.per = rtvISDBT_GetPER() * 3125;
isdbt_signal_info.rssi = rtvISDBT_GetRSSI() / RTV_ISDBT_RSSI_DIVIDER;
if (copy_to_user(argp, &isdbt_signal_info, sizeof(IOCTL_ISDBT_SIGNAL_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_LGE_GET_TUNER_INFO:
//
lge_tuner_info.LOCK = rtvISDBT_GetLockStatus() == RTV_ISDBT_CHANNEL_LOCK_OK ? 1: 0;
lge_tuner_info.CNo = rtvISDBT_GetCNR() / RTV_ISDBT_CNR_DIVIDER;
lge_tuner_info.CNo = 10 * lge_tuner_info.CNo;
lge_tuner_info.BER = rtvISDBT_GetBER();
if(lge_tuner_info.BER > 1500)
lge_tuner_info.BER = 100000;
lge_tuner_info.PER = rtvISDBT_GetPER() * 3125;
#if 1
if(lge_tuner_info.LOCK == 0)
lge_tuner_info.BER = lge_tuner_info.PER = 100000;
#endif
lge_tuner_info.AGC= rtvISDBT_GetAGC();
lge_tuner_info.RSSI= rtvISDBT_GetRSSI() / RTV_ISDBT_RSSI_DIVIDER;
// temp!!!!
lge_tuner_info.start_ts_int_cnt = mtv250_cb_ptr->start_ts_int_cnt;
lge_tuner_info.ovf_err_cnt = mtv250_cb_ptr->ovf_err_cnt;
if (copy_to_user(argp, &lge_tuner_info, sizeof(IOCTL_ISDBT_LGE_TUNER_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_ISDBT_START_TS:
RTV_GUARD_LOCK;
mtv250_cb_ptr->start_ts_int_cnt = 0;
mtv250_cb_ptr->ovf_err_cnt = 0;
mtv250_cb_ptr->max_read_jiffies = 0;
rtv_StreamEnable();
RTV_GUARD_FREE;
break;
case IOCTL_ISDBT_STOP_TS:
rtvISDBT_DisableStreamOut();
mtv250_reset_tsp();
break;
case IOCTL_TEST_DMB_POWER_ON:
DMBMSG("[mtv250_ioctl] IOCTL_TEST_DMB_POWER_ON\n");
RTV_MASTER_CHIP_SEL;
rtvOEM_PowerOn(1);
mtv250_cb_ptr->is_power_on = TRUE;
break;
case IOCTL_TEST_DMB_POWER_OFF:
RTV_MASTER_CHIP_SEL;
rtvOEM_PowerOn(0);
mtv250_cb_ptr->is_power_on = FALSE;
break;
case IOCTL_REGISTER_READ:
if(mtv250_cb_ptr->is_power_on == FALSE)
{
DMBMSG("[mtv] Power Down state!Must Power ON\n");
ret = -EFAULT;
goto IOCTL_EXIT;
}
if (copy_from_user(&ioctl_register_access, argp, sizeof(RTV_IOCTL_REGISTER_ACCESS)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
//DMBMSG("[mtv] IOCTL_REGISTER_READ: [%d] 0x%02X\n", ioctl_register_access.page, ioctl_register_access.Addr);
switch( mtv250_cb_ptr->tv_mode )
{
case DMB_TV_MODE_TDMB:
case DMB_TV_MODE_FM:
switch( ioctl_register_access.page )
{
case 6: reg_page = 0x06; break; // OFDM
case 7: reg_page = 0x09; break; // FEC
case 8: reg_page = 0x0A; break; // FEC
default: reg_page = mtv_reg_page_addr[ioctl_register_access.page];
}
break;
case DMB_TV_MODE_1SEG:
switch( ioctl_register_access.page )
{
case 6: reg_page = 0x02; break; // OFDM
case 7: reg_page = 0x03; break; // FEC
default: reg_page = mtv_reg_page_addr[ioctl_register_access.page];
}
break;
default: break;
}
RTV_REG_MAP_SEL(reg_page);
ioctl_register_access.data[0] = RTV_REG_GET(ioctl_register_access.Addr);
if (copy_to_user(argp, &ioctl_register_access, sizeof(RTV_IOCTL_REGISTER_ACCESS)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
case IOCTL_REGISTER_WRITE:
if(mtv250_cb_ptr->is_power_on == FALSE)
{
DMBMSG("[mtv] Power Down state!Must Power ON\n");
ret = -EFAULT;
goto IOCTL_EXIT;
}
if (copy_from_user(&ioctl_register_access, argp, sizeof(RTV_IOCTL_REGISTER_ACCESS)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
switch( mtv250_cb_ptr->tv_mode )
{
case DMB_TV_MODE_TDMB:
case DMB_TV_MODE_FM:
switch( ioctl_register_access.page )
{
case 6: reg_page = 0x06; break; // OFDM
case 7: reg_page = 0x09; break; // FEC
case 8: reg_page = 0x0A; break; // FEC
default: reg_page = mtv_reg_page_addr[ioctl_register_access.page];
}
break;
case DMB_TV_MODE_1SEG:
switch( ioctl_register_access.page )
{
case 6: reg_page = 0x02; break; // OFDM
case 7: reg_page = 0x03; break; // FEC
default: reg_page = mtv_reg_page_addr[ioctl_register_access.page];
}
break;
default: break;
}
RTV_REG_MAP_SEL(reg_page);
RTV_REG_SET(ioctl_register_access.Addr, ioctl_register_access.data[0]);
break;
case IOCTL_TEST_GPIO_SET:
if(mtv250_cb_ptr->is_power_on == FALSE)
{
DMBMSG("[mtv] Power Down state!Must Power ON\n");
ret = -EFAULT;
goto IOCTL_EXIT;
}
if (copy_from_user(&gpio_info, argp, sizeof(RTV_IOCTL_TEST_GPIO_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
gpio_set_value(gpio_info.pin, gpio_info.value);
break;
case IOCTL_TEST_GPIO_GET:
if(mtv250_cb_ptr->is_power_on == FALSE)
{
DMBMSG("[mtv] Power Down state!Must Power ON\n");
ret = -EFAULT;
goto IOCTL_EXIT;
}
if (copy_from_user(&gpio_info, argp, sizeof(RTV_IOCTL_TEST_GPIO_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
gpio_info.value = gpio_get_value(gpio_info.pin);
if(copy_to_user(argp, &gpio_info, sizeof(RTV_IOCTL_TEST_GPIO_INFO)))
{
ret = -EFAULT;
goto IOCTL_EXIT;
}
break;
default:
DMBERR("[mtv] Invalid ioctl command: %d\n", cmd);
ret = -ENOTTY;
break;
}
IOCTL_EXIT:
return ret;
}
