static void rtl8192_after_radio_check(struct net_device *dev, bool rf_state, bool turnonbypowerdomain)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
if (turnonbypowerdomain) {
PHY_SetRtl8192seRfHalt(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
}
#ifdef CONFIG_ASPM_OR_D3
if (!rf_state) {
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_ASPM) {
RT_ENABLE_ASPM(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_ASPM);
}
#ifdef TODO
else if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_PCI_D3) {
RT_ENTER_D3(dev, false);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_PCI_D3);
}
#endif
}
#endif
return;
}
void rtl8192_hw_sleep_down(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
unsigned long flags = 0;
#ifdef CONFIG_ASPM_OR_D3
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
#endif
spin_lock_irqsave(&priv->rf_ps_lock,flags);
if (priv->RFChangeInProgress) {
spin_unlock_irqrestore(&priv->rf_ps_lock,flags);
RT_TRACE(COMP_RF, "rtl8192_hw_sleep_down(): RF Change in progress! \n");
printk("rtl8192_hw_sleep_down(): RF Change in progress!\n");
return;
}
spin_unlock_irqrestore(&priv->rf_ps_lock,flags);
RT_TRACE(COMP_PS, "%s()============>come to sleep down\n", __FUNCTION__);
#ifdef CONFIG_RTLWIFI_DEBUGFS
if(priv->debug->hw_holding) {
return;
}
#endif
MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS,false);
#ifdef CONFIG_ASPM_OR_D3
if(pPSC->RegRfPsLevel & RT_RF_LPS_LEVEL_ASPM)
{
RT_ENABLE_ASPM(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_LPS_LEVEL_ASPM);
}
#endif
}
static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
ppsc->b_swrf_processing = true;
if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) {
if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM) &&
rtlhal->interface == INTF_PCI) {
rtlpriv->intf_ops->disable_aspm(hw);
RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
}
stg_rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate,
RF_CHANGE_BY_IPS, false);
if (ppsc->inactive_pwrstate == ERFOFF &&
rtlhal->interface == INTF_PCI) {
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
!RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
}
ppsc->b_swrf_processing = false;
}
void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 sleep_intv;
if (!rtlpriv->psc.sw_ps_enabled)
return;
if ((rtlpriv->sec.being_setkey) ||
(mac->opmode == NL80211_IFTYPE_ADHOC))
return;
/*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
if ((mac->link_state != MAC80211_LINKED) || (mac->cnt_after_linked < 5))
return;
if (rtlpriv->link_info.busytraffic)
return;
mutex_lock(&rtlpriv->locks.ps_mutex);
rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS);
mutex_unlock(&rtlpriv->locks.ps_mutex);
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
!RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
/* here is power save alg, when this beacon is DTIM
* we will set sleep time to dtim_period * n;
* when this beacon is not DTIM, we will set sleep
* time to sleep_intv = rtlpriv->psc.dtim_counter or
* MAX_SW_LPS_SLEEP_INTV(default set to 5) */
if (rtlpriv->psc.dtim_counter == 0) {
if (hw->conf.ps_dtim_period == 1)
sleep_intv = hw->conf.ps_dtim_period * 2;
else
sleep_intv = hw->conf.ps_dtim_period;
} else {
sleep_intv = rtlpriv->psc.dtim_counter;
}
if (sleep_intv > MAX_SW_LPS_SLEEP_INTV)
sleep_intv = MAX_SW_LPS_SLEEP_INTV;
/* this print should always be dtim_conter = 0 &
* sleep = dtim_period, that meaons, we should
* awake before every dtim */
RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
"dtim_counter:%x will sleep :%d beacon_intv\n",
rtlpriv->psc.dtim_counter, sleep_intv);
/* we tested that 40ms is enough for sw & hw sw delay */
queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq,
MSECS(sleep_intv * mac->vif->bss_conf.beacon_int - 40));
}
void rtl92su_card_disable(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
enum nl80211_iftype opmode;
u8 wait = 30;
rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
/* this is very important for ips power save */
while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
if (rtlpriv->psc.pwrdomain_protect)
mdelay(20);
else
break;
}
mac->link_state = MAC80211_NOLINK;
opmode = NL80211_IFTYPE_UNSPECIFIED;
rtl92s_set_media_status(hw, opmode);
rtl92s_phy_set_rfhalt(hw);
udelay(100);
}
void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 sleep_intv;
if (!rtlpriv->psc.sw_ps_enabled)
return;
if ((rtlpriv->sec.being_setkey) ||
(mac->opmode == NL80211_IFTYPE_ADHOC))
return;
if ((mac->link_state != MAC80211_LINKED) || (mac->cnt_after_linked < 5))
return;
if (rtlpriv->link_info.busytraffic)
return;
mutex_lock(&rtlpriv->locks.ps_mutex);
rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS);
mutex_unlock(&rtlpriv->locks.ps_mutex);
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
!RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
rtlpriv->intf_ops->enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
}
if (rtlpriv->psc.dtim_counter == 0) {
if (hw->conf.ps_dtim_period == 1)
sleep_intv = hw->conf.ps_dtim_period * 2;
else
sleep_intv = hw->conf.ps_dtim_period;
} else {
sleep_intv = rtlpriv->psc.dtim_counter;
}
if (sleep_intv > MAX_SW_LPS_SLEEP_INTV)
sleep_intv = MAX_SW_LPS_SLEEP_INTV;
RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
"dtim_counter:%x will sleep :%d beacon_intv\n",
rtlpriv->psc.dtim_counter, sleep_intv);
queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq,
MSECS(sleep_intv * mac->vif->bss_conf.beacon_int - 40));
}
static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
{
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
_rtl_pci_update_default_setting(hw);
if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
/*Always enable ASPM & Clock Req. */
rtl_pci_enable_aspm(hw);
RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
}
}
/*
*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
*power saving We should follow the sequence to enable
*RTL8192SE first then enable Pci Bridge ASPM
*or the system will show bluescreen.
*/
static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
u16 aspmlevel;
u8 u_pcibridge_aspmsetting;
u8 u_device_aspmsetting;
if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
("PCI(Bridge) UNKNOWN.\n"));
return;
}
/*4 Enable Pci Bridge ASPM */
rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
pcicfg_addrport + (num4bytes << 2));
u_pcibridge_aspmsetting =
pcipriv->ndis_adapter.pcibridge_linkctrlreg |
rtlpci->const_hostpci_aspm_setting;
if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
u_pcibridge_aspmsetting &= ~BIT(0);
rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
("PlatformEnableASPM():PciBridge busnumber[%x], "
"DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
(pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
u_pcibridge_aspmsetting));
udelay(50);
/*Get ASPM level (with/without Clock Req) */
aspmlevel = rtlpci->const_devicepci_aspm_setting;
u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
/*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
/*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
u_device_aspmsetting |= aspmlevel;
_rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
_rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
}
udelay(200);
}
static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
bool bresult = true;
u8 i, queue_id;
struct rtl8192_tx_ring *ring = NULL;
ppsc->set_rfpowerstate_inprogress = true;
switch (rfpwr_state) {
case ERFON:{
if ((ppsc->rfpwr_state == ERFOFF) &&
RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus;
u32 InitializeCount = 0;
do {
InitializeCount++;
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
("IPS Set eRf nic enable\n"));
rtstatus = rtl_ps_enable_nic(hw);
} while ((rtstatus != true)
&& (InitializeCount < 10));
RT_CLEAR_PS_LEVEL(ppsc,
RT_RF_OFF_LEVL_HALT_NIC);
} else {
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
("Set ERFON sleeped:%d ms\n",
jiffies_to_msecs(jiffies -
ppsc->
last_sleep_jiffies)));
ppsc->last_awake_jiffies = jiffies;
rtl92ce_phy_set_rf_on(hw);
}
if (mac->link_state == MAC80211_LINKED) {
rtlpriv->cfg->ops->led_control(hw,
LED_CTL_LINK);
} else {
rtlpriv->cfg->ops->led_control(hw,
LED_CTL_NO_LINK);
}
break;
}
case ERFOFF:{
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
("IPS Set eRf nic disable\n"));
rtl_ps_disable_nic(hw);
RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
} else {
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
rtlpriv->cfg->ops->led_control(hw,
LED_CTL_NO_LINK);
} else {
rtlpriv->cfg->ops->led_control(hw,
LED_CTL_POWER_OFF);
}
}
break;
}
case ERFSLEEP:{
if (ppsc->rfpwr_state == ERFOFF)
return false;
for (queue_id = 0, i = 0;
queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
ring = &pcipriv->dev.tx_ring[queue_id];
if (skb_queue_len(&ring->queue) == 0) {
queue_id++;
continue;
} else {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
("eRf Off/Sleep: %d times "
"TcbBusyQueue[%d] =%d before "
"doze!\n", (i + 1), queue_id,
skb_queue_len(&ring->queue)));
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
("\n ERFSLEEP: %d times "
"TcbBusyQueue[%d] = %d !\n",
MAX_DOZE_WAITING_TIMES_9x,
queue_id,
skb_queue_len(&ring->queue)));
break;
}
}
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
("Set ERFSLEEP awaked:%d ms\n",
jiffies_to_msecs(jiffies -
ppsc->last_awake_jiffies)));
ppsc->last_sleep_jiffies = jiffies;
_rtl92ce_phy_set_rf_sleep(hw);
break;
}
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
("switch case not process\n"));
bresult = false;
break;
}
if (bresult)
ppsc->rfpwr_state = rfpwr_state;
ppsc->set_rfpowerstate_inprogress = false;
return bresult;
}
void PlatformEnableASPM(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC =
(PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
u16 ASPMLevel = 0;
u32 PciCfgAddrPort=0;
u8 Num4Bytes;
u8 uPciBridgeASPMSetting = 0;
u8 uDeviceASPMSetting = 0;
if( (priv->NdisAdapter.BusNumber == 0xff &&
priv->NdisAdapter.DevNumber == 0xff &&
priv->NdisAdapter.FuncNumber == 0xff) ||
(priv->NdisAdapter.PciBridgeBusNum == 0xff &&
priv->NdisAdapter.PciBridgeDevNum == 0xff &&
priv->NdisAdapter.PciBridgeFuncNum == 0xff) ) {
RT_TRACE(COMP_INIT, "PlatformEnableASPM(): Fail to enable ASPM."
" Cannot find the Bus of PCI(Bridge).\n");
return;
}
#ifdef RTL8192SE
if(priv->NdisAdapter.PciBridgeVendor != PCI_BRIDGE_VENDOR_INTEL) {
RT_TRACE(COMP_POWER, "%s(): Dont modify ASPM for non intel "
"chipset. For Bridge Vendor %d.\n"
,__func__,priv->NdisAdapter.PciBridgeVendor);
return;
}
#endif
#ifdef RTL8192CE
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11) |
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg |
priv->RegHostPciASPMSetting;
if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL)
uPciBridgeASPMSetting &= ~ BIT0;
NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting);
RT_TRACE(COMP_INIT, "PlatformEnableASPM():PciBridge BusNumber[%x], "
"DevNumbe[%x], FuncNumber[%x], Write reg[%x] = %x\n",
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
uPciBridgeASPMSetting);
udelay(50);
#endif
ASPMLevel |= priv->RegDevicePciASPMSetting;
uDeviceASPMSetting = priv->NdisAdapter.LinkCtrlReg;
#ifdef RTL8192SE
if(priv->CustomerID == RT_CID_TOSHIBA &&
priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD) {
if(priv->NdisAdapter.LinkCtrlReg & BIT1)
uDeviceASPMSetting |= BIT0;
else
uDeviceASPMSetting |= ASPMLevel;
}
else
#endif
uDeviceASPMSetting |= ASPMLevel;
PlatformSwitchDevicePciASPM(dev, uDeviceASPMSetting);
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) {
PlatformSwitchClkReq(dev,(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_CLK_REQ);
}
udelay(100);
#ifdef RTL8192SE
PciCfgAddrPort= (priv->NdisAdapter.PciBridgeBusNum << 16)|
(priv->NdisAdapter.PciBridgeDevNum<< 11)|
(priv->NdisAdapter.PciBridgeFuncNum << 8)|(1 << 31);
Num4Bytes = (priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10)/4;
NdisRawWritePortUlong(PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
uPciBridgeASPMSetting = priv->NdisAdapter.PciBridgeLinkCtrlReg |
priv->RegHostPciASPMSetting;
if(priv->CustomerID == RT_CID_TOSHIBA &&
priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_AMD
&& pPSC->RegAMDPciASPM) {
if(priv->NdisAdapter.PciBridgeLinkCtrlReg & BIT1)
uPciBridgeASPMSetting |= BIT0;
} else if(priv->NdisAdapter.PciBridgeVendor == PCI_BRIDGE_VENDOR_INTEL ) {
uPciBridgeASPMSetting &= ~ BIT0;
}
NdisRawWritePortUchar(PCI_CONF_DATA, uPciBridgeASPMSetting);
RT_TRACE(COMP_INIT, "%s:PciBridge BusNumber[%x], DevNumbe[%x], "
"FuncNumber[%x], Write reg[%x] = %x\n",__func__,
priv->NdisAdapter.PciBridgeBusNum,
priv->NdisAdapter.PciBridgeDevNum,
priv->NdisAdapter.PciBridgeFuncNum,
(priv->NdisAdapter.PciBridgePCIeHdrOffset+0x10),
uPciBridgeASPMSetting);
#endif
udelay(100);
}
void InactivePsWorkItemCallback(struct net_device *dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->rtllib->PowerSaveControl));
RT_TRACE(COMP_PS, "InactivePsWorkItemCallback() ---------> \n");
pPSC->bSwRfProcessing = true;
RT_TRACE(COMP_PS, "InactivePsWorkItemCallback(): Set RF to %s.\n", \
pPSC->eInactivePowerState == eRfOff?"OFF":"ON");
#ifdef CONFIG_ASPM_OR_D3
if(pPSC->eInactivePowerState == eRfOn)
{
if((pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_ASPM) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_ASPM))
{
RT_DISABLE_ASPM(dev);
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_ASPM);
}
#ifdef TODO
else if((pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_PCI_D3) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_PCI_D3))
{
RT_LEAVE_D3(dev, false);
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_PCI_D3);
}
#endif
}
#endif
MgntActSet_RF_State(dev, pPSC->eInactivePowerState, RF_CHANGE_BY_IPS,false);
#ifdef CONFIG_ASPM_OR_D3
if(pPSC->eInactivePowerState == eRfOff)
{
if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_ASPM)
{
RT_ENABLE_ASPM(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_ASPM);
}
#ifdef TODO
else if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_PCI_D3)
{
RT_ENTER_D3(dev, false);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_PCI_D3);
}
#endif
}
#endif
#if 0
if(pPSC->eInactivePowerState == eRfOn)
{
while( index < 4 )
{
if( ( pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP104_Encryption ) ||
(pMgntInfo->SecurityInfo.PairwiseEncAlgorithm == WEP40_Encryption) )
{
if( pMgntInfo->SecurityInfo.KeyLen[index] != 0)
pAdapter->HalFunc.SetKeyHandler(pAdapter, index, 0, false, pMgntInfo->SecurityInfo.PairwiseEncAlgorithm, true, false);
}
index++;
}
}
#endif
pPSC->bSwRfProcessing = false;
RT_TRACE(COMP_PS, "InactivePsWorkItemCallback() <--------- \n");
}
static bool
SetRFPowerState8190(
struct net_device* dev,
RT_RF_POWER_STATE eRFPowerState
)
{
struct r8192_priv *priv = ieee80211_priv(dev);
PRT_POWER_SAVE_CONTROL pPSC = (PRT_POWER_SAVE_CONTROL)(&(priv->ieee80211->PowerSaveControl));
bool bResult = true;
//u8 eRFPath;
u8 i = 0, QueueID = 0;
//ptx_ring head=NULL,tail=NULL;
struct rtl8192_tx_ring *ring = NULL;
if(priv->SetRFPowerStateInProgress == true)
return false;
//RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
priv->SetRFPowerStateInProgress = true;
switch(priv->rf_chip)
{
case RF_8256:
switch( eRFPowerState )
{
case eRfOn:
//RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n");
//RXTX enable control: On
//for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
// PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x2);
#ifdef RTL8190P
if(priv->rf_type == RF_2T4R)
{
//enable RF-Chip A/B
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
//enable RF-Chip C/D
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
//digital to analog on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e0, 0xf); // 0x880[8:5]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0xf);// 0xc04[3:0]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0xf);// 0xd04[3:0]
//analog to digital part2 on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1e00, 0xf); // 0x880[12:9]
}
else if(priv->rf_type == RF_1T2R) //RF-C, RF-D
{
//enable RF-Chip C/D
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
//digital to analog on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x180, 0x3); // 0x880[8:7]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xc, 0x3);// 0xc04[3:2]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xc, 0x3);// 0xd04[3:2]
//analog to digital part2 on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x1800, 0x3); // 0x880[12:11]
}
else if(priv->rf_type == RF_1T1R) //RF-C
{
//enable RF-Chip C/D
rtl8192_setBBreg(dev, rFPGA0_XC_RFInterfaceOE, BIT4, 0x1); // 0x868[4]
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x400, 0x1);// 0x88c[10]
//digital to analog on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x80, 0x1); // 0x880[7]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x4, 0x1);// 0xc04[2]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x4, 0x1);// 0xd04[2]
//analog to digital part2 on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x800, 0x1); // 0x880[11]
}
#elif defined RTL8192E
// turn on RF
if((priv->ieee80211->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{ // The current RF state is OFF and the RF OFF level is halting the NIC, re-initialize the NIC.
bool rtstatus = true;
u32 InitializeCount = 3;
do
{
InitializeCount--;
priv->RegRfOff = false;
rtstatus = NicIFEnableNIC(dev);
}while( (rtstatus != true) &&(InitializeCount >0) );
if(rtstatus != true)
{
RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__FUNCTION__);
priv->SetRFPowerStateInProgress = false;
return false;
}
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else {
write_nic_byte(dev, ANAPAR, 0x37);//160MHz
//write_nic_byte(dev, MacBlkCtrl, 0x17); // 0x403
mdelay(1);
//enable clock 80/88 MHz
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
priv->bHwRfOffAction = 0;
//}
//RF-A, RF-B
//enable RF-Chip A/B
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
//analog to digital on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
//digital to analog on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
//rx antenna on
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
//analog to digital part2 on
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
// Baseband reset 2008.09.30 add
//write_nic_byte(dev, BB_RESET, (read_nic_byte(dev, BB_RESET)|BIT0));
//2 AFE
// 2008.09.30 add
//rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0x20000000, 0x1); // 0x884
//analog to digital part2 on
//rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
//digital to analog on
//rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x98, 0x13); // 0x880[4:3]
//analog to digital on
//rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf03, 0xf03);// 0x88c[9:8]
//rx antenna on
//PHY_SetBBReg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
//rx antenna on 2008.09.30 mark
//PHY_SetBBReg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
//2 RF
//enable RF-Chip A/B
//rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
//rtl8192_setBBreg(dev, rFPGA0_XB_RFInterfaceOE, BIT4, 0x1); // 0x864[4]
}
#endif
break;
//
// In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
// By Bruce, 2008-01-16.
//
case eRfSleep:
{
// HW setting had been configured with deeper mode.
if(priv->ieee80211->eRFPowerState == eRfOff)
break;
// Update current RF state variable.
//priv->ieee80211->eRFPowerState = eRFPowerState;
//if (pPSC->bLeisurePs)
{
for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
{
ring = &priv->tx_ring[QueueID];
if(skb_queue_len(&ring->queue) == 0)
{
QueueID++;
continue;
}
else
{
RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
udelay(10);
i++;
}
if(i >= MAX_DOZE_WAITING_TIMES_9x)
{
RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
}
}
}
//if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
#ifdef RTL8190P
{
PHY_SetRtl8190pRfOff(dev);
}
//else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
#elif defined RTL8192E
{
PHY_SetRtl8192eRfOff(dev);
}
#endif
}
break;
case eRfOff:
//RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n");
// Update current RF state variable.
//priv->ieee80211->eRFPowerState = eRFPowerState;
//
// Disconnect with Any AP or STA.
//
for(QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; )
{
ring = &priv->tx_ring[QueueID];
if(skb_queue_len(&ring->queue) == 0)
{
QueueID++;
continue;
}
else
{
RT_TRACE(COMP_POWER,
"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
udelay(10);
i++;
}
if(i >= MAX_DOZE_WAITING_TIMES_9x)
{
RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
}
}
//if(Adapter->HardwareType == HARDWARE_TYPE_RTL8190P)
#if defined RTL8190P
{
PHY_SetRtl8190pRfOff(dev);
}
//else if(Adapter->HardwareType == HARDWARE_TYPE_RTL8192E)
#elif defined RTL8192E
{
//if(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC) && priv->ieee80211->RfOffReason > RF_CHANGE_BY_PS)
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{ // Disable all components.
//
// Note:
// NicIFSetLinkStatus is a big problem when we indicate the status to OS,
// the OS(XP) will reset. But now, we cnnot find why the NIC is hard to receive
// packets after RF ON. Just keep this function here and still work to find out the root couse.
// By Bruce, 2009-05-01.
//
//NicIFSetLinkStatus( Adapter, RT_MEDIA_DISCONNECT );
//if HW radio of , need to indicate scan complete first for not be reset.
//if(MgntScanInProgress(pMgntInfo))
// MgntResetScanProcess( Adapter );
// <1> Disable Interrupt
//rtl8192_irq_disable(dev);
// <2> Stop all timer
//MgntCancelAllTimer(Adapter);
// <3> Disable Adapter
//NicIFHaltAdapter(Adapter, false);
NicIFDisableNIC(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
}
else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
{ // Normal case.
// IPS should go to this.
PHY_SetRtl8192eRfOff(dev);
}
}
#else
else
{
RT_TRACE(COMP_DBG,DBG_TRACE,("It is not 8190Pci and 8192PciE \n"));
}
#endif
break;
default:
bResult = false;
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
break;
}
break;
default:
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
break;
}
static bool _rtl92e_set_rf_power_state(struct net_device *dev,
enum rt_rf_power_state eRFPowerState)
{
struct r8192_priv *priv = rtllib_priv(dev);
struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
(&(priv->rtllib->PowerSaveControl));
bool bResult = true;
u8 i = 0, QueueID = 0;
struct rtl8192_tx_ring *ring = NULL;
if (priv->SetRFPowerStateInProgress)
return false;
RT_TRACE(COMP_PS, "===========> _rtl92e_set_rf_power_state()!\n");
priv->SetRFPowerStateInProgress = true;
switch (priv->rf_chip) {
case RF_8256:
switch (eRFPowerState) {
case eRfOn:
RT_TRACE(COMP_PS,
"_rtl92e_set_rf_power_state() eRfOn!\n");
if ((priv->rtllib->eRFPowerState == eRfOff) &&
RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus = true;
u32 InitilizeCount = 3;
do {
InitilizeCount--;
priv->RegRfOff = false;
rtstatus = rtl92e_enable_nic(dev);
} while (!rtstatus && (InitilizeCount > 0));
if (!rtstatus) {
netdev_err(dev,
"%s(): Failed to initialize Adapter.\n",
__func__);
priv->SetRFPowerStateInProgress = false;
return false;
}
RT_CLEAR_PS_LEVEL(pPSC,
RT_RF_OFF_LEVL_HALT_NIC);
} else {
rtl92e_writeb(dev, ANAPAR, 0x37);
mdelay(1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x4, 0x1);
priv->bHwRfOffAction = 0;
rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
BIT4, 0x1);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
0x300, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x18, 0x3);
rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
0x3, 0x3);
rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
0x60, 0x3);
}
break;
case eRfSleep:
if (priv->rtllib->eRFPowerState == eRfOff)
break;
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
RT_TRACE((COMP_POWER|COMP_RF),
"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
(i+1), QueueID);
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x) {
RT_TRACE(COMP_POWER,
"\n\n\n TimeOut!! _rtl92e_set_rf_power_state(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
MAX_DOZE_WAITING_TIMES_9x,
QueueID);
break;
}
}
rtl92e_set_rf_off(dev);
break;
case eRfOff:
RT_TRACE(COMP_PS,
"_rtl92e_set_rf_power_state() eRfOff/Sleep !\n");
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++;
continue;
} else {
RT_TRACE(COMP_POWER,
"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
(i+1), QueueID);
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x) {
RT_TRACE(COMP_POWER,
"\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
MAX_DOZE_WAITING_TIMES_9x,
QueueID);
break;
}
}
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
!RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
rtl92e_disable_nic(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else if (!(pPSC->RegRfPsLevel &
RT_RF_OFF_LEVL_HALT_NIC)) {
rtl92e_set_rf_off(dev);
}
break;
default:
bResult = false;
netdev_warn(dev,
"%s(): Unknown state requested: 0x%X.\n",
__func__, eRFPowerState);
break;
}
break;
default:
netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
break;
}
if (bResult) {
priv->rtllib->eRFPowerState = eRFPowerState;
switch (priv->rf_chip) {
case RF_8256:
break;
default:
netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
break;
}
}
priv->SetRFPowerStateInProgress = false;
RT_TRACE(COMP_PS,
"<=========== _rtl92e_set_rf_power_state() bResult = %d!\n",
bResult);
return bResult;
}
static bool SetRFPowerState8190(struct r8192_priv *priv,
RT_RF_POWER_STATE eRFPowerState)
{
PRT_POWER_SAVE_CONTROL pPSC = &priv->PowerSaveControl;
bool bResult = true;
if (eRFPowerState == priv->eRFPowerState &&
priv->bHwRfOffAction == 0) {
bResult = false;
goto out;
}
switch( eRFPowerState )
{
case eRfOn:
// turn on RF
if ((priv->eRFPowerState == eRfOff) &&
RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
/*
* The current RF state is OFF and the RF OFF level
* is halting the NIC, re-initialize the NIC.
*/
if (!NicIFEnableNIC(priv)) {
RT_TRACE(COMP_ERR, "%s(): NicIFEnableNIC failed\n",__FUNCTION__);
bResult = false;
goto out;
}
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} else {
write_nic_byte(priv, ANAPAR, 0x37);//160MHz
mdelay(1);
//enable clock 80/88 MHz
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x4, 0x1); // 0x880[2]
priv->bHwRfOffAction = 0;
//RF-A, RF-B
//enable RF-Chip A/B
rtl8192_setBBreg(priv, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4]
//analog to digital on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
//digital to analog on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
//rx antenna on
rtl8192_setBBreg(priv, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
//rx antenna on
rtl8192_setBBreg(priv, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
//analog to digital part2 on
rtl8192_setBBreg(priv, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
}
break;
//
// In current solution, RFSleep=RFOff in order to save power under 802.11 power save.
// By Bruce, 2008-01-16.
//
case eRfSleep:
// HW setting had been configured with deeper mode.
if(priv->eRFPowerState == eRfOff)
break;
r8192e_drain_tx_queues(priv);
PHY_SetRtl8192eRfOff(priv);
break;
case eRfOff:
//
// Disconnect with Any AP or STA.
//
r8192e_drain_tx_queues(priv);
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
/* Disable all components. */
NicIFDisableNIC(priv);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
}
else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
{
/* Normal case - IPS should go to this. */
PHY_SetRtl8192eRfOff(priv);
}
break;
default:
bResult = false;
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState);
break;
}
if(bResult)
{
// Update current RF state variable.
priv->eRFPowerState = eRFPowerState;
}
out:
return bResult;
}
bool rtl92su_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
bool bresult = true;
if (rfpwr_state == ppsc->rfpwr_state)
return false;
switch (rfpwr_state) {
case ERFON:{
if ((ppsc->rfpwr_state == ERFOFF) &&
RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
bool rtstatus;
u32 InitializeCount = 0;
do {
InitializeCount++;
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
"IPS Set eRf nic enable\n");
rtstatus = rtl_ps_enable_nic(hw);
} while (!rtstatus && (InitializeCount < 10));
RT_CLEAR_PS_LEVEL(ppsc,
RT_RF_OFF_LEVL_HALT_NIC);
} else {
RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
"awake, slept:%d ms state_inap:%x\n",
jiffies_to_msecs(jiffies -
ppsc->
last_sleep_jiffies),
rtlpriv->psc.state_inap);
ppsc->last_awake_jiffies = jiffies;
rtl_write_word(rtlpriv, CMDR, 0x37FC);
rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
rtl_write_byte(rtlpriv, REG_RFPGA0_CCA, 0x3);
rtl_write_byte(rtlpriv, REG_SPS1_CTRL, 0x64);
}
break;
}
case ERFOFF:{
if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
"IPS Set eRf nic disable\n");
rtl_ps_disable_nic(hw);
RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
}
break;
}
case ERFSLEEP:
if (ppsc->rfpwr_state == ERFOFF)
return false;
RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
"Set ERFSLEEP awaked:%d ms\n",
jiffies_to_msecs(jiffies -
ppsc->last_awake_jiffies));
RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
"sleep awaked:%d ms state_inap:%x\n",
jiffies_to_msecs(jiffies -
ppsc->last_awake_jiffies),
rtlpriv->psc.state_inap);
ppsc->last_sleep_jiffies = jiffies;
rtl92s_phy_set_rf_sleep(hw);
break;
default:
pr_err("switch case %#x not processed\n", rfpwr_state);
bresult = false;
break;
}
if (bresult)
ppsc->rfpwr_state = rfpwr_state;
return bresult;
}
