std::string Interval::toString() {
std::ostringstream out;
auto delim = "";
if (reg.isGP()) {
out << reg::regname(Reg64(reg));
delim = " ";
} else if (reg.isSIMD()) {
out << reg::regname(RegXMM(reg));
delim = " ";
}
if (cns) {
out << delim << folly::format("#{:08x}", val);
}
if (slot >= 0) {
out << delim << "[%rsp+" << PhysLoc::disp(slot) << "]";
}
delim = "";
out << " [";
for (auto r : ranges) {
out << delim << folly::format("{}-{}", r.start, r.end);
delim = ",";
}
out << ") {";
delim = "";
for (auto u : uses) {
out << delim << u.pos;
delim = ",";
}
out << "}";
return out.str();
}
std::string show(PhysReg r) {
switch (arch()) {
case Arch::X64:
return r.type() == PhysReg::GP ? reg::regname(Reg64(r)) :
r.type() == PhysReg::SIMD ? reg::regname(RegXMM(r)) :
/* r.type() == PhysReg::SF) ? */ reg::regname(RegSF(r));
case Arch::ARM:
if (r.isSF()) return "SF";
return folly::to<std::string>(
r.isGP() ? (vixl::Register(r).size() == vixl::kXRegSize ? 'x' : 'w')
: (vixl::FPRegister(r).size() == vixl::kSRegSize ? 's' : 'd'),
((vixl::CPURegister)r).code()
);
case Arch::PPC64:
return r.type() == PhysReg::GP ? ppc64_asm::reg::regname(Reg64(r)) :
r.type() == PhysReg::SIMD ? ppc64_asm::reg::regname(RegXMM(r)) :
/* r.type() == PhysReg::SF) ? */ ppc64_asm::reg::regname(RegSF(r));
}
not_reached();
}
void Assembler::stdu(const Reg64& rt, MemoryRef m) {
assertx(Reg64(-1) == m.r.index); // doesn't support base+index
EmitDSForm(62, rn(rt), rn(m.r.base), m.r.disp, 1);
}
void Assembler::lhz(const Reg64& rt, MemoryRef m) {
assertx(Reg64(-1) == m.r.index); // doesn't support base+index
EmitDForm(40, rn(rt), rn(m.r.base), m.r.disp);
}
