//------------------------------------------------------------------------------
// Function Name: SiI_CEC_GetCommand
// Function Description: This function gets data from CEC Reception
//
// Accepts: pSiI_CEC
// Returns: none
// Globals: none
//------------------------------------------------------------------------------
uint8_t SiI_CEC_GetCommand( SiI_CEC_t * pSiI_CEC )
{
uint8_t error = FALSE;
uint8_t bCount;
bCount = pSiI_CEC->bCount & 0x0f; // extract uint8_t counter, ignore frame counter
if ( !(pSiI_CEC->bCount & BIT_MSG_ERROR) )
RegisterReadBlock(REG__CEC_RX_CMD_HEADER, &pSiI_CEC->bDestOrRXHeader , bCount + 2);
else
error = 1;
// Clear CLR_RX_FIFO_CUR;
// Clear current frame from Rx FIFO
RegisterModify(REG__CEC_RX_CONTROL, BIT_CLR_RX_FIFO_CUR, BIT_CLR_RX_FIFO_CUR );
// Check if more frame in Rx FIFO, if yes get uint8_t count of next frame.
pSiI_CEC->bRXNextCount = 0;
if( pSiI_CEC->bCount & 0xF0 )
{
pSiI_CEC->bRXNextCount = RegisterRead(REG__CEC_RX_COUNT);
}
return error;
}
int sii_get_vs_to_de(void)
{
unsigned char low;
low = RegisterRead(REG__VID_VS_AVT)&MSK__VID_VS_AVT_BIT0_5;
return low;
}
int sii_get_pwr5v_status(void)
{
char pwr5v;
pwr5v = RegisterRead(REG__STATE)&BIT__PWR5V;
return (pwr5v==0)?0:1;
}
char sii_get_hdmi_port(void)
{
char port;
port = RegisterRead(REG__PORT_SWTCH2);
return (port&MSK__PORT_EN);
}
int sii_get_vs_frontporch(void)
{
unsigned char low;
low = RegisterRead(REG__VID_V_FP)&MSK__VID_V_FP_BIT0_5;
return low;
}
// audio sampling frequency:
// 0x0 for 44.1 KHz
// 0x1 for Not indicated
// 0x2 for 48 KHz
// 0x3 for 32 KHz
// 0x4 for 22.05 KHz
// 0x6 for 24 kHz
// 0x8 for 88.2 kHz
// 0x9 for 768 kHz (192*4)
// 0xa for 96 kHz
// 0xc for 176.4 kHz
// 0xe for 192 kHz
int sii_get_audio_sampling_freq(void)
{
unsigned char freq;
freq = RegisterRead(REG__AUD_CHST4)&BIT__AUD_FS;
return freq;
}
int sii_is_hdmi_mode(void)
{
unsigned char mode;
mode = RegisterRead(REG__AUDP_STAT)&BIT__HDMI_DET;
mode = (mode==0)?0:1;
return mode;
}
/**
* @brief 通讯发送数据处理函数
* @param comm : 通讯对象
* @param head : 数据头指针
* @retval 是否成功处理了数据包
*/
bool NaviPack_TxProcessor(NavipackComm_Type *comm, NaviPack_HeadType *head)
{
switch(head->functionCode)
{
case FUNC_ID_READ_USER:
// TODO: 用户寄存器数据发送
// RegisterRead(comm, head, 0, (u8*)&UserReg, sizeof(UserReg), REG_ID_USER);
break;
case FUNC_ID_READ_STATUS:
return RegisterRead(comm, head, 0, (u8*)&comm->status, sizeof(comm->status), REG_ID_STATUS);
case FUNC_ID_READ_CONTROL:
return RegisterRead(comm, head, 0, (u8*)&comm->control, sizeof(comm->control), REG_ID_COTROL);
case FUNC_ID_READ_CONFIG:
return RegisterRead(comm, head, 0, (u8*)&comm->config, sizeof(comm->config), REG_ID_CONFIG);
}
return false;
}
status_t
ArchMailboxArmBCM2835::Write(uint8 channel, uint32 value)
{
// We have to wait for the mailbox to drain if it is marked full.
while ((RegisterRead(ARM_MAILBOX_STATUS) & ARM_MAILBOX_FULL) != 0)
;
value &= ARM_MAILBOX_DATA_MASK;
RegisterWrite(ARM_MAILBOX_WRITE, value | channel);
return B_OK;
}
status_t
ArchMailboxArmBCM2835::Read(uint8 channel, uint32& value)
{
while (true) {
// Wait for something to arrive in the mailbox.
if ((RegisterRead(ARM_MAILBOX_STATUS) & ARM_MAILBOX_EMPTY) != 0)
continue;
value = RegisterRead(ARM_MAILBOX_READ);
if ((value & ARM_MAILBOX_CHANNEL_MASK) != channel) {
// Not for us, retry.
continue;
}
break;
}
value &= ARM_MAILBOX_DATA_MASK;
return B_OK;
}
//------------------------------------------------------------------------------
// Function: AcpPacketHandler
// Description: disable digital output for ACP type 2 and above
//
//------------------------------------------------------------------------------
static void AcpPacketHandler(uint8_t qOn)
{
//disable SPIDF when ACP type >=2 For simply test.
if((qOn)&&(RegisterRead(REG__ACP_BYTE2) > 1))
{
RegisterWrite(REG__AUD_CTRL, (CONF__AUD_CTRL&(~BIT__SPEN)));
DEBUG_PRINT(("ACP type > 1, digital output blocked\n"));
}
else
RegisterWrite(REG__AUD_CTRL, CONF__AUD_CTRL);
}
uint8_t PclkCheck(void)
{
uint8_t xpcnt0_0;
uint8_t xpcnt1_0;
uint8_t xpcnt0_1;
uint8_t xpcnt1_1;
uint8_t wrongzone = 0;
if((RegisterRead(REG__STATE))&BIT__PCLK_STABLE) //pclk stable
{
xpcnt0_0 = RegisterRead(0x06E);
xpcnt1_0 = RegisterRead(0x06F);
RegisterWrite(0x069,0x80); //change base
// DEBUG_PRINT(("full cnt=%02X %02X ",(int)xpcnt0_0, (int)xpcnt1_0));
xpcnt0_1 = RegisterRead(0x06E);
xpcnt1_1 = RegisterRead(0x06F);
// DEBUG_PRINT(("half cnt=%02X %02X\n",(int)xpcnt0_1, (int)xpcnt1_1));
RegisterWrite(0x069,0xFF);
if((xpcnt0_0==xpcnt0_1)&&(xpcnt1_0 <= xpcnt1_1)) //if xpcnt changes
wrongzone=1;
else
return TRUE;
}
else
{
wrongzone=1;
}
if(wrongzone==1)
{
DEBUG_PRINT(("pclk stopped"));
TurnVideoMute(ON);
CurrentStatus.ColorDepth = 0;
RegisterModify(REG__TMDS_CCTRL2, MSK__DC_CTL, VAL__DC_CTL_8BPP_1X);
}
return FALSE;
}
static uint8_t ProcessVhResolutionChange(void)
{
if (CurrentStatus.ResolutionChangeCount++ == 10)
{
CurrentStatus.ResolutionChangeCount = 0;
DEBUG_PRINT((" **** VHreschng\n"));
if((RegisterRead(REG__FACTORY_A88)&0x0F)>=0x02) //not 1x zone
ResetZoneControl();
return TRUE;
}
return FALSE;
}
//------------------------------------------------------------------------------
// Function: SetUpAudioOutput
// Description: Setup registers for audio output formatting for each format (PCM, DSD, HBR)
// Each frmat has its own unique MCLK value.
// Only PCM and DSD support multi channel output.
//
// Notes: Compile time configuration is done using CONF__* defines in config.h
//------------------------------------------------------------------------------
static void SetUpAudioOutput(void)
{
uint8_t bAudioStatus;
bAudioStatus = RegisterRead(REG__AUDP_STAT);
if (bAudioStatus & BIT__DSD_STATUS) //DSD Audio
{
if(CurrentStatus.AudioMode!=AUDIO_MODE__DSD)
{
CurrentStatus.AudioMode = AUDIO_MODE__DSD;
RegisterWrite(REG__I2S_CTRL1, CONF__DSD__I2S_CTRL1);
if (bAudioStatus & BIT__HDMI_LO) //layout = 1, enable multi channel
RegisterWrite(REG__I2S_CTRL2, CONF__DSD__I2S_CTRL2__LAYOUT_1 | BIT__MCLKEN); //enable MCLK
else //layout = 0, enable 2 channel only
RegisterWrite(REG__I2S_CTRL2, CONF__DSD__I2S_CTRL2__LAYOUT_0 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("DSD aud\n"));
}
}
else if (bAudioStatus & BIT__HBRA_ON) //HBR Audio
{
CurrentStatus.AudioMode = AUDIO_MODE__HBR;
RegisterWrite(REG__I2S_CTRL1, CONF__HBR__I2S_CTRL1);
RegisterWrite(REG__I2S_CTRL2, CONF__HBR__I2S_CTRL2 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("HBR aud\n"));
}
else
{
if(CurrentStatus.AudioMode!=AUDIO_MODE__PCM)
{
CurrentStatus.AudioMode = AUDIO_MODE__PCM;
RegisterWrite(REG__I2S_CTRL1, CONF__PCM__I2S_CTRL1);
if (bAudioStatus & BIT__HDMI_LO) //layout = 1, enable multi channel
RegisterWrite(REG__I2S_CTRL2, CONF__PCM__I2S_CTRL2__LAYOUT_1 | BIT__MCLKEN); //enable MCLK
else //layout = 0, enable 2 channel only
RegisterWrite(REG__I2S_CTRL2, CONF__PCM__I2S_CTRL2__LAYOUT_0 | BIT__MCLKEN); //enable MCLK
DEBUG_PRINT(("PCM aud\n"));
}
}
}
static void ConfigureDeepColor(void)
{
uint8_t abDcCtlVal1x[] = { VAL__DC_CTL_8BPP_1X, VAL__DC_CTL_10BPP_1X, VAL__DC_CTL_12BPP_1X, 0 };
uint8_t abDcCtlVal2x[] = { VAL__DC_CTL_8BPP_2X, VAL__DC_CTL_10BPP_2X, VAL__DC_CTL_12BPP_2X, 0 };
uint8_t bColorDepth;
uint8_t bDcCtlValue;
uint8_t vStatus;
bColorDepth = RegisterRead(REG__DC_STAT) & MSK__PIXEL_DEPTH;
if (bColorDepth != CurrentStatus.ColorDepth)
{
if(CurrentStatus.VideoState == STATE_VIDEO__ON)
vStatus = ON;
CurrentStatus.ColorDepth = bColorDepth;
if(vStatus == ON)
TurnVideoMute(ON);
//value is 2x if muxYC output is enabled
if (RegisterRead(REG__VID_AOF) & BIT__MUXYC)
{
bDcCtlValue = abDcCtlVal2x[ bColorDepth ];
}
else
{
bDcCtlValue = abDcCtlVal1x[ bColorDepth ];
}
RegisterModify(REG__TMDS_CCTRL2, MSK__DC_CTL, bDcCtlValue);
RegisterBitToggle(REG__SRST2, BIT__DCFIFO_RST); //reset the deep color FIFO
DEBUG_PRINT(("DC stat=%02X ctl=%02X\n", (int)bColorDepth, (int)bDcCtlValue));
if(vStatus == ON)
TurnVideoMute(OFF);
}
}
static uint8_t ConfigureZone(void)
{
if((RegisterRead(REG__STATE))&BIT__PCLK_STABLE) //pclk stable
{
return TRUE;
}
else
{
DEBUG_PRINT((" **** pclk not stable\n"));
ResetZoneControl();
}
return FALSE;
}
//------------------------------------------------------------------------------
// Function Name: SiI_918x_Start
// Function Description: Intilize Stream Switch Device
// CEC Software Connection #1
//------------------------------------------------------------------------------
//void SiI_918x_Start( void )
void CEC_Init( void )
{
// uint8_t cec_phyAddr[2];
#if(CONF__CEC_ENABLE == ENABLE)
DEBUG_PRINT(("\nStream switch start\n"));
//CEC workaround for ES0
GPIO_ClearCecD();
RegisterModify(REG__CEC_CONFIG_CPI,BIT__CEC_PASS_THROUGH,CLEAR);
if((RegisterRead(DEV_REV_RX)& 0x0F)==VAL__REV_1_2) //if rev1.2 CEC by default reset
RegisterModify(REG__C0_SRST2, BIT__CEC_SRST, SET); //0 is reset, 1 is normal
else
RegisterBitToggle(REG__C0_SRST2,BIT__CEC_SRST);
RegisterWrite(REG__SLAVE_ADDR_EDID,CONF__I2C_SLAVE_PAGE_9);
RegisterWrite(REG__SLAVE_ADDR_CEC,CONF__I2C_SLAVE_PAGE_8);
// Set CEC device type = TV and logical address to capture.
InitiatorAddress = CEC_LOGADDR_UNREGORBC_MSG ;
if( CEC_CAPTURE_ID_Set( InitiatorAddress ) )
{
DEBUG_PRINT(("\n Cannot init CEC"));
}
//
// 4. Initialize Event Descriptor
//
CEC_event_descriptor_clear();
// Enumirate as an TV
bCECTask = SiI_CEC_Enumiration;
bEnumType = SiI_EnumTV;
#endif // #if(CONF__CEC_ENABLE == ENABLE)
//====================
// 5. Program EDID and set port specific address space.
// Program (a) EDID and (b) Physical address
//====================
ProgramEDID();
}
static void ProcessScdtModeChange(void)
{
uint8_t bStateReg;
static uint8_t current_scdt = 0;
bStateReg = RegisterRead(REG__STATE); //read scdt off or on
if (bStateReg & BIT__SCDT) //SCDT on
{
//mute the audio if it is still on, it happens when SCDT off and on in a very short time
if(CurrentStatus.AudioState == STATE_AUDIO__ON)
{
TurnAudioMute(ON);
CurrentStatus.AudioState = STATE_AUDIO__MUTED;
}
CurrentStatus.ColorDepth = 0;
RegisterModify(REG__TMDS_CCTRL2, MSK__DC_CTL, VAL__DC_CTL_8BPP_1X);
CurrentStatus.ResolutionChangeCount = 0;
CurrentStatus.VideoStabilityCheckCount = 0;
CurrentStatus.AudioState = STATE_AUDIO__REQUEST_AUDIO;
RegisterModify(REG__ECC_CTRL, BIT__CAPCNT, SET); //clear the error cont
CurrentStatus.VideoState = STATE_VIDEO__UNMUTE;
TIMER_Set(TIMER__VIDEO, VIDEO_UNMUTE_TIMEOUT); // start the video timer
HdmiInitIf(); //yma add for 3D packet support
printk("sii9233a SCDT on!\n");
if( current_scdt == 0 )
{
sii9233a_output_mode_trigger(1);
current_scdt = 1;
}
}
else //SCDT off
{
TurnVideoMute(ON);
printk("sii9233a SCDT off!\n");
if( current_scdt == 1 )
{
sii9233a_output_mode_trigger(0);
current_scdt = 0;
}
}
}
//------------------------------------------------------------------------------
// Function: ResetVideoControl
// Description:
// Note: check pclk status to configure the zone
//------------------------------------------------------------------------------
uint8_t ResetVideoControl(void)
{
if(RegisterRead(REG__HDMI_MUTE)&BIT__VIDM_STATUS)
{
DEBUG_PRINT(("reset video control\n"));
TurnVideoMute(ON);
CurrentStatus.ColorDepth = 0;
RegisterModify(REG__TMDS_CCTRL2, MSK__DC_CTL, VAL__DC_CTL_8BPP_1X);
ResetZoneControl();
return FALSE;
}
else //video unmute status OK
{
TurnVideoMute(OFF);
return TRUE;
}
}
//------------------------------------------------------------------------------
// Function: AudioUnmuteHandler
// Description: State machine for performing audio unmute in firmware.
//------------------------------------------------------------------------------
void AudioUnmuteHandler(void)
{
uint8_t bIntrStatus2;
uint8_t bIntrStatus4;
RegisterModify(REG__ECC_CTRL, BIT__CAPCNT, SET); //clear the error cont
switch (CurrentStatus.AudioState)
{
case STATE_AUDIO__REQUEST_AUDIO:
{
bIntrStatus2 = RegisterRead(REG__INTR2);
bIntrStatus4 = RegisterRead(REG__INTR4);
if ((bIntrStatus2 & BIT__GOTAUD) && (bIntrStatus2 & BIT__GOTCTS)) //audio stable
{
if(bIntrStatus4 & MSK__CTS_ERROR)
// reset ACR
RegisterBitToggle(REG__SRST, BIT__ACRRST);
else
{
// init ACR
RegisterWrite(REG__ACR_CTRL1, BIT__ACR_INIT);
DEBUG_PRINT(("aud rdy\n"));
SetUpAudioOutput();
CurrentStatus.AudioState = STATE_AUDIO__AUDIO_READY;
}
}
// clear all the audio interrupts
RegisterWrite(REG__INTR2, (BIT__GOTAUD | BIT__GOTCTS));
RegisterWrite(REG__INTR4, (MSK__CTS_ERROR | MSK__FIFO_ERROR));
TIMER_Set(TIMER__AUDIO, 20); // delay 20ms before request audio again
}
break;
case STATE_AUDIO__AUDIO_READY:
{
bIntrStatus4 = RegisterRead(REG__INTR4);
if(bIntrStatus4 & MSK__CTS_ERROR)
CurrentStatus.AudioState = STATE_AUDIO__REQUEST_AUDIO;
else if (!(bIntrStatus4 & MSK__FIFO_ERROR)) // no audio FIFO error
{
if ((CurrentStatus.VideoState == STATE_VIDEO__ON)
||(CurrentStatus.VideoState == STATE_VIDEO__CHECKED))
//||ResetVideoControl())//video unmute status ok
{
if(CurrentStatus.AudioMode==AUDIO_MODE__DSD)
HAL_SetAudioDACMode(AUDIO_MODE__DSD);
else
HAL_SetAudioDACMode(AUDIO_MODE__PCM);
RegisterWrite(REG__INTR5, MSK__AUDIO_INTR);// clear all audio interrupts
CurrentStatus.AudioState = STATE_AUDIO__ON;
TurnAudioMute(OFF);
}
}
else
{
// reset audio FIFO
RegisterBitToggle(REG__SRST, BIT__FIFORST);
// clear audio FIFO interrupts
RegisterWrite(REG__INTR4, MSK__FIFO_ERROR);
TIMER_Set(TIMER__AUDIO, 20); // delay 20ms before ready audio again
}
}
}
}
static uint8_t GetIfTypeFromUnreqBuffer ( void ){
return RegisterRead( REG__UNREQ_TYPE );
}
static uint8_t GetMpegDecodeAddr ( void ){
return RegisterRead( REG__MPEG_DECODE);
}
//------------------------------------------------------------------------------
// Function Name: SiI_CEC_IntProcessing
// Function Description: This function is called on interrupt events
// it makes interrut service
// Accepts: SiI_CEC_Int_t * pInt
// Returns: none
// Globals: none
//------------------------------------------------------------------------------
uint8_t CEC_IntProcessing ( SiI_CEC_Int_t * pInt )
{
uint8_t error = FALSE;
uint8_t cec_int_status_reg[2];
// Get Interrupts
pInt->bTXState = 0;
pInt->bCECErrors = 0;
pInt->bRXState = 0;
RegisterReadBlock(REG__CEC_INT_STATUS_0,cec_int_status_reg,2);
{
// Poll Interrupt
if( (cec_int_status_reg[0] & 0x7F) || cec_int_status_reg[1] )
{
DEBUG_PRINT(("\nA6A7Reg: %02X %02X", (int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// Clear interrupts
if ( cec_int_status_reg[1] & BIT_FRAME_RETRANSM_OV )
{
DEBUG_PRINT(("\n!CEC_A7_TX_RETRY_EXCEEDED![%02X][%02X]",(int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// flash TX otherwise after writing clear interrupt
// BIT_FRAME_RETRANSM_OV the TX command will be re-send
RegisterModify(REG__CEC_DEBUG_3,BIT_FLUSH_TX_FIFO, BIT_FLUSH_TX_FIFO);
}
//
// Clear set bits that are set
//
RegisterWriteBlock(REG__CEC_INT_STATUS_0,cec_int_status_reg,2);
DEBUG_PRINT(("\nA6A7Reg: %02X %02X", (int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// RX Processing
if ( cec_int_status_reg[0] & BIT_RX_MSG_RECEIVED )
{
// Save number of frames in Rx Buffer
pInt->bRXState = RegisterRead(REG__CEC_RX_COUNT);
}
// RX Errors processing
if ( cec_int_status_reg[1] & BIT_SHORT_PULSE_DET )
{
pInt->bCECErrors |= eSiI_CEC_ShortPulse;
}
if ( cec_int_status_reg[1] & BIT_START_IRREGULAR )
{
pInt->bCECErrors |= eSiI_CEC_StartIrregular;
}
if ( cec_int_status_reg[1] & BIT_RX_FIFO_OVERRUN ) // fixed per Uematsu san
{
pInt->bCECErrors |= eSiI_CEC_RXOverFlow;
}
// TX Processing
if ( cec_int_status_reg[0] & BIT_TX_FIFO_EMPTY ) //0x04
{
pInt->bTXState = eSiI_TXWaitCmd;
}
if ( cec_int_status_reg[0] & BIT_TX_MESSAGE_SENT ) //0x20
{
pInt->bTXState = eSiI_TXSendAcked;
}
if ( cec_int_status_reg[1] & BIT_FRAME_RETRANSM_OV ) //0x02
{
pInt->bTXState = eSiI_TXFailedToSend;
}
}
}
return error;
}
