// // Enable sleep state transition // VOID FchEnableSleepTransition ( VOID ) { // Set SLP_TYPEn to enable SLP_TYP to do S1/S3/S5 RwPmio (FCH_PMIOA_REGBE, AccessWidth8, 0xFF, BIT5, NULL); // Enable S state transition RwPmio (FCH_PMIOA_REG08 + 3, AccessWidth8, (UINT32)~(BIT1 + BIT0), (UINT32) BIT0, NULL); }
/** * ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID ProgramFchHwAcpiResetP ( IN VOID *FchDataPtr ) { FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader); RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader); RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader); RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader); }
/** * ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID ProgramFchHwAcpiResetP ( IN VOID *FchDataPtr ) { FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader); RwPmio (0xD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader); if ( LocalCfgPtr->Cg2Pll == 1 ) { TurnOffCG2 (); LocalCfgPtr->SataClkMode = 0x0a; } }
/** * FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary * ) during Power-On * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitResetHwAcpiP ( IN VOID *FchDataPtr ) { FCH_RESET_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; // // Enabled (Mmio_mem_enable) // RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader); ProgramFchHwAcpiResetP (FchDataPtr); RwPmio (0xD2, AccessWidth8, (UINT32)~BIT6, 0, StdHeader); }
/** * FchInitLateUsb - Config USB controller before OS Boot * emulation * * * * @param[in] FchDataPtr Fch configuration structure pointer. * */ VOID FchInitLateUsb ( IN VOID *FchDataPtr ) { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; /// UBTS368324 RPR 7.35 Device swapping in S3 RwPmio (FCH_PMIOA_REGF4, AccessWidth8, ~(UINT32) BIT0, BIT0, StdHeader); }