static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
printk("bs pdev->id=%d %s %s:%d",pdev->id,__func__,__FILE__,__LINE__);//
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_PCM0_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_PCM0_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_PCM0_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_PCM0_SIN);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_PCM0_SOUT);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_PCM1_SCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_PCM1_EXTCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_PCM1_FSYNC);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_PCM1_SIN);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_PCM1_SOUT);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
switch (dai->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_DO);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_DO);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0);
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1);
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2);
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI);
break;
}
return 0;
}
static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power)
gpio_direction_output(S3C64XX_GPE(0), 1);
else
gpio_direction_output(S3C64XX_GPE(0), 0);
}
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_AC97_BITCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_AC97_nRESET);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_AC97_SYNC);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_AC97_SDI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_AC97_SDO);
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
struct device *dev = &pdev->dev;
struct s3c_i2sv2_info *i2s;
int ret;
dev_dbg(dev, "%s: probing dai %d\n", __func__, pdev->id);
if (pdev->id < 0 || pdev->id > ARRAY_SIZE(s3c64xx_i2s)) {
dev_err(dev, "id %d out of range\n", pdev->id);
return -EINVAL;
}
i2s = &s3c64xx_i2s[pdev->id];
ret = s3c_i2sv2_probe(pdev, dai, i2s,
pdev->id ? S3C64XX_PA_IIS1 : S3C64XX_PA_IIS0);
if (ret)
return ret;
i2s->dma_capture = &s3c64xx_i2s_pcm_stereo_in[pdev->id];
i2s->dma_playback = &s3c64xx_i2s_pcm_stereo_out[pdev->id];
i2s->iis_cclk = clk_get(dev, "audio-bus");
if (IS_ERR(i2s->iis_cclk)) {
dev_err(dev, "failed to get audio-bus");
iounmap(i2s->regs);
return -ENODEV;
}
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
}
return 0;
}
static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(5));
return 0;
default:
printk(KERN_DEBUG "Invalid I2S Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0;
}
static int s3c64xx_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
/* configure GPIO for i2s port */
switch (dai->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
}
return 0;
}
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0);
default:
printk(KERN_DEBUG "Invalid I2S Controller number!");
return -EINVAL;
}
return 0;
}
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{
unsigned int base;
switch (pdev->id) {
case 0:
base = S3C64XX_GPD(0);
break;
case 1:
base = S3C64XX_GPE(0);
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number: %d\n",
pdev->id);
return -EINVAL;
}
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0;
}
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPG(0),
.ngpio = S3C64XX_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S3C64XX_GPM_BASE,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
}
static int s3c_i2s_probe(struct platform_device *pdev,
struct snd_soc_dai *dai)
{
int ret = 0;
struct clk *cm, *cf;
debug_msg("%s\n", __FUNCTION__);
/* Configure the I2S pins in correct mode */
#ifndef CONFIG_SND_S3C64XX_I2S_BUS1
s3c_gpio_cfgpin(S3C64XX_GPD(0),S3C64XX_GPD0_I2S0_CLK);
s3c_gpio_cfgpin(S3C64XX_GPD(1),S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(2),S3C64XX_GPD2_I2S0_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3),S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4),S3C64XX_GPD4_I2S0_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPD(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(4), S3C_GPIO_PULL_UP);
#else
s3c_gpio_cfgpin(S3C64XX_GPE(0),S3C64XX_GPE0_I2S1_CLK);
s3c_gpio_cfgpin(S3C64XX_GPE(1),S3C64XX_GPE1_I2S1_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(2),S3C64XX_GPE2_I2S1_LRCLK);
s3c_gpio_cfgpin(S3C64XX_GPE(3),S3C64XX_GPE3_I2S1_DI);
s3c_gpio_cfgpin(S3C64XX_GPE(4),S3C64XX_GPE4_I2S1_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPE(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPE(4), S3C_GPIO_PULL_UP);
#endif
s3c_i2s.regs = ioremap(S3C_IIS_PABASE, 0x100);
if (s3c_i2s.regs == NULL)
return -ENXIO;
ret = request_irq(S3C_IISIRQ, s3c_iis_irq, 0, "s3c-i2s", pdev);
if (ret < 0) {
printk("fail to claim i2s irq , ret = %d\n", ret);
iounmap(s3c_i2s.regs);
return -ENODEV;
}
printk("pd name=%s\n", pdev->name);
s3c_i2s.iis_clk = clk_get(&pdev->dev, PCLKCLK);
if (IS_ERR(s3c_i2s.iis_clk)) {
printk("failed to get clk(%s)\n", PCLKCLK);
goto lb5;
}
clk_enable(s3c_i2s.iis_clk);
s3c_i2s.clk_rate = clk_get_rate(s3c_i2s.iis_clk);
debug_msg("s3c_i2s.clk_rate1=%d\n",s3c_i2s.clk_rate);
#ifdef USE_CLKAUDIO
s3c_i2s.audio_bus = clk_get(NULL, EXTCLK);
if (IS_ERR(s3c_i2s.audio_bus)) {
printk("failed to get clk(%s)\n", EXTCLK);
goto lb4;
}
cm = clk_get(NULL, "mout_epll");
if (IS_ERR(cm)) {
printk("failed to get mout_epll\n");
goto lb3;
}
if(clk_set_parent(s3c_i2s.audio_bus, cm)){
printk("failed to set MOUTepll as parent of CLKAUDIO0\n");
goto lb2;
}
cf = clk_get(NULL, "fout_epll");
if (IS_ERR(cf)) {
printk("failed to get fout_epll\n");
goto lb2;
}
clk_enable(cf);
if(clk_set_parent(cm, cf)){
printk("failed to set FOUTepll as parent of MOUTepll\n");
goto lb1;
}
s3c_i2s.clk_rate = clk_get_rate(s3c_i2s.audio_bus);
clk_put(cf);
clk_put(cm);
#endif
debug_msg("s3c_i2s.clk_rate2=%d\n",s3c_i2s.clk_rate);
writel(S3C_IISCON_I2SACTIVE | S3C_IISCON_SWRESET, s3c_i2s.regs + S3C_IISCON);
s3c_snd_txctrl(0);
s3c_snd_rxctrl(0);
return 0;
#ifdef USE_CLKAUDIO
lb1:
clk_put(cf);
lb2:
clk_put(cm);
lb3:
clk_put(s3c_i2s.audio_bus);
#endif
lb4:
clk_disable(s3c_i2s.iis_clk);
clk_put(s3c_i2s.iis_clk);
lb5:
free_irq(S3C_IISIRQ, pdev);
iounmap(s3c_i2s.regs);
return -ENODEV;
}
ssize_t dev_read(struct file *filp,char __user *buf,size_t count,loff_t *f_pos)
{
*buf = gpio_get_value(S3C64XX_GPE(1));
return 1;
}
ssize_t dev_open(struct inode *inode,struct file *filep)
{
/* Configure GPE(1) ad input mode */
s3c_gpio_cfgpin(S3C64XX_GPE(1),0x0);
return 0;
}
int s3cfb_set_gpio(void)
{
unsigned long val;
int i, err;
#if 0
/* See mach-smdk6410.c:smdk6410_map_io() - S3C64XX_MODEM_MIFPCON */
/* Must be '0' for Normal-path instead of By-pass */
writel(0x0, S3C_HOSTIFB_MIFPCON);
#endif
/* enable clock to LCD */
val = readl(S3C_HCLK_GATE);
val |= S3C_CLKCON_HCLK_LCD;
writel(val, S3C_HCLK_GATE);
/* select TFT LCD type (RGB I/F) */
val = readl(S3C64XX_SPCON);
val &= ~0x3;
val |= (1 << 0);
writel(val, S3C64XX_SPCON);
/* VD */
for (i = 0; i < 16; i++)
s3c_gpio_cfgpin(S3C64XX_GPI(i), S3C_GPIO_SFN(2));
for (i = 0; i < 12; i++)
s3c_gpio_cfgpin(S3C64XX_GPJ(i), S3C_GPIO_SFN(2));
/* backlight ON */
//printk("oPEN LCD BACKLIGHT1.\n");
if (gpio_is_valid(S3C64XX_GPF(14))) { //NOTE: orign GPF15 here
err = gpio_request(S3C64XX_GPF(14), "GPF");
if (err) {
printk(KERN_ERR "failed to request GPF for "
"lcd backlight control\n");
return err;
}
gpio_direction_output(S3C64XX_GPF(14), 1);
gpio_set_value(S3C64XX_GPF(14), 1);
}
//printk("oPEN LCD BACKLIGHT2.\n");
if (gpio_is_valid(S3C64XX_GPE(0))) {
err = gpio_request(S3C64XX_GPE(0), "GPE");
if (err) {
printk(KERN_ERR "failed to request GPE for "
"lcd reset control\n");
return err;
}
gpio_direction_output(S3C64XX_GPE(0), 1);
}
gpio_set_value(S3C64XX_GPE(0), 1);
gpio_free(S3C64XX_GPE(0));
/* module reset */
/*if (gpio_is_valid(S3C64XX_GPN(5))) {
err = gpio_request(S3C64XX_GPN(5), "GPN");
if (err) {
printk(KERN_ERR "failed to request GPN for "
"lcd reset control\n");
return err;
}
gpio_direction_output(S3C64XX_GPN(5), 1);
}
mdelay(100);
gpio_set_value(S3C64XX_GPN(5), 0);
mdelay(10);
gpio_set_value(S3C64XX_GPN(5), 1);
mdelay(10);
*/
#ifndef CONFIG_BACKLIGHT_PWM
gpio_free(S3C64XX_GPF(14));
#endif
//gpio_free(S3C64XX_GPN(5));
return 0;
}
static struct platform_device ok6410_gpio_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &gpio_button_data,
}
};
/**
* gpio_ir_recv need a pin that could triger IRQ, but the pin connected to ir
* receiver on ok6410 is GPE1 which doesn't have that function. So this ir device
* actually not work yet. We may consider using other pin like GPMx instead.
*/
static struct gpio_ir_recv_platform_data ok6410_gpio_ir_recv_data = {
.gpio_nr = S3C64XX_GPE(1),
.active_low = false,
};
static struct platform_device ok6410_gpio_ir_recv = {
.name = "gpio-rc-recv",
.num_resources = 0,
.dev.platform_data = &ok6410_gpio_ir_recv_data,
};
/* framebuffer and LCD setup. */
/* GPF15 = LCD backlight control
* GPF13 => Panel power
* GPN5 = LCD nRESET signal
* PWM_TOUT1 => backlight brightness
