/**
* BSC entry point for for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
* @param[in] CpbServices The current CPU's family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] EntryPoint Current CPU feature dispatch point.
* @param[in] StdHeader Config handle for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F15CzInitializeCpb (
IN CPB_FAMILY_SERVICES *CpbServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN UINT64 EntryPoint,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPB_CTRL_REGISTER CpbControl;
PCI_ADDR PciAddress;
PCI_ADDR StcPciAddr;
F15_PSTATE_MSR PstateMsrData;
SW_PS_LIMIT_REGISTER Stc;
UINT32 Pbx;
UINT32 PsMax;
if ((EntryPoint & CPU_FEAT_MID_INIT) != 0) {
PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
if (CpbControl.BoostSrc == 0) {
// If any boosted P-state is still enabled, set BoostSrc = 1.
for (Pbx = 0; Pbx < CpbControl.NumBoostStates; Pbx++) {
LibAmdMsrRead (PS_REG_BASE + Pbx, (UINT64 *)&PstateMsrData, StdHeader);
if (PstateMsrData.PsEnable == 1) {
StcPciAddr.AddressValue = SW_PS_LIMIT_PCI_ADDR;
LibAmdPciRead (AccessWidth32, StcPciAddr, &Stc, StdHeader);
Stc.SwPstateLimitEn = 1;
Stc.SwPstateLimit = CpbControl.NumBoostStates;
LibAmdPciWrite (AccessWidth32, StcPciAddr, &Stc, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, StcPciAddr, AccessWidth32, &Stc);
CpbControl.BoostSrc = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &CpbControl);
break;
}
}
}
} else if ((EntryPoint & CPU_FEAT_MID_LATE_INIT) != 0) {
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0xDC);
LibAmdPciRead (AccessWidth32, PciAddress, &PsMax, StdHeader);
PsMax = ((PsMax & 0x700) << 20);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 3, 0x68);
LibAmdPciWrite (AccessWidth32, PciAddress, &PsMax, StdHeader);
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, AccessWidth32, &PsMax);
}
return AGESA_SUCCESS;
}
/**
* Write PCI registers
*
*
*
* @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
* @param[in] Width Access width
* @param[in] Value Pointer to value
* @param[in] StdHeader Pointer to standard header
*/
VOID
GnbLibPciWrite (
IN UINT32 Address,
IN ACCESS_WIDTH Width,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PciAddress.AddressValue = Address;
if (Width >= AccessS3SaveWidth8) {
S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value);
}
LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
}
