/*
* External camera reset
* Because the most of cameras take i2c bus signal, so that
* you have to reset at the boot time for other i2c slave devices.
* This function also called at fimc_init_camera()
* Do optimization for cameras on your platform.
*/
void cam0_s5k4eagx_reset(int power_up)
{
#define S5PC11X_GPH0 S5PV210_GPH0
#define S5PC11X_GPH1 S5PV210_GPH1
#define S5PC11X_GPE1 S5PV210_GPE1
printk(KERN_INFO "s5k4eagx reset\n");
gpio_request(S5PC11X_GPE1(4), "GPE14");
gpio_direction_output(S5PC11X_GPE1(4), 1);
gpio_request(S5PC11X_GPH0(2), "GPH02");
gpio_direction_output(S5PC11X_GPH0(2), 1);
if(power_up)
{
//reset --> L
gpio_set_value(S5PC11X_GPH0(2), 0);
//STBY --> HIGH
gpio_set_value(S5PC11X_GPE1(4), 1);
mdelay(5);
//reset --> H
gpio_set_value(S5PC11X_GPH0(2), 1);
}
else //power down
{
//reset --> L
gpio_set_value(S5PC11X_GPH0(2), 0);
mdelay(5);
//STBY --> LOW
gpio_set_value(S5PC11X_GPE1(4), 0);
}
gpio_free(S5PC11X_GPE1(4));
gpio_free(S5PC11X_GPH0(2));
}
void s3c_fimc0_cfg_gpio(struct platform_device *pdev)
{
int i;
s3c_gpio_cfgpin(S5PC11X_GPE0(0), S5PC11X_GPE0_0_CAM_A_PCLK);
s3c_gpio_cfgpin(S5PC11X_GPE0(1), S5PC11X_GPE0_1_CAM_A_VSYNC);
s3c_gpio_cfgpin(S5PC11X_GPE0(2), S5PC11X_GPE0_2_CAM_A_HREF);
s3c_gpio_cfgpin(S5PC11X_GPE0(3), S5PC11X_GPE0_3_CAM_A_DATA_0);
s3c_gpio_cfgpin(S5PC11X_GPE0(4), S5PC11X_GPE0_4_CAM_A_DATA_1);
s3c_gpio_cfgpin(S5PC11X_GPE0(5), S5PC11X_GPE0_5_CAM_A_DATA_2);
s3c_gpio_cfgpin(S5PC11X_GPE0(6), S5PC11X_GPE0_6_CAM_A_DATA_3);
s3c_gpio_cfgpin(S5PC11X_GPE0(7), S5PC11X_GPE0_7_CAM_A_DATA_4);
s3c_gpio_cfgpin(S5PC11X_GPE1(0), S5PC11X_GPE1_0_CAM_A_DATA_5);
s3c_gpio_cfgpin(S5PC11X_GPE1(1), S5PC11X_GPE1_1_CAM_A_DATA_6);
s3c_gpio_cfgpin(S5PC11X_GPE1(2), S5PC11X_GPE1_2_CAM_A_DATA_7);
s3c_gpio_cfgpin(S5PC11X_GPE1(3), S5PC11X_GPE1_3_CAM_A_CLKOUT);
s3c_gpio_cfgpin(S5PC11X_GPE1(4), S5PC11X_GPE1_4_CAM_A_FIELD);
for (i = 0; i < 8; i++)
s3c_gpio_setpull(S5PC11X_GPE0(i), S3C_GPIO_PULL_NONE);
for (i = 0; i < 5; i++)
s3c_gpio_setpull(S5PC11X_GPE1(i), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S5PC11X_GPJ0(0), S5PC11X_GPJ0_0_CAM_B_DATA_0);
s3c_gpio_cfgpin(S5PC11X_GPJ0(1), S5PC11X_GPJ0_1_CAM_B_DATA_1);
s3c_gpio_cfgpin(S5PC11X_GPJ0(2), S5PC11X_GPJ0_2_CAM_B_DATA_2);
s3c_gpio_cfgpin(S5PC11X_GPJ0(3), S5PC11X_GPJ0_3_CAM_B_DATA_3);
s3c_gpio_cfgpin(S5PC11X_GPJ0(4), S5PC11X_GPJ0_4_CAM_B_DATA_4);
s3c_gpio_cfgpin(S5PC11X_GPJ0(5), S5PC11X_GPJ0_5_CAM_B_DATA_5);
s3c_gpio_cfgpin(S5PC11X_GPJ0(6), S5PC11X_GPJ0_6_CAM_B_DATA_6);
s3c_gpio_cfgpin(S5PC11X_GPJ0(7), S5PC11X_GPJ0_7_CAM_B_DATA_7);
s3c_gpio_cfgpin(S5PC11X_GPJ1(0), S5PC11X_GPJ1_0_CAM_B_PCLK);
s3c_gpio_cfgpin(S5PC11X_GPJ1(1), S5PC11X_GPJ1_1_CAM_B_VSYNC);
s3c_gpio_cfgpin(S5PC11X_GPJ1(2), S5PC11X_GPJ1_2_CAM_B_HREF);
s3c_gpio_cfgpin(S5PC11X_GPJ1(3), S5PC11X_GPJ1_3_CAM_B_FIELD);
s3c_gpio_cfgpin(S5PC11X_GPJ1(4), S5PC11X_GPJ1_4_CAM_B_CLKOUT);
for (i = 0; i < 8; i++)
s3c_gpio_setpull(S5PC11X_GPJ0(i), S3C_GPIO_PULL_NONE);
for (i = 0; i < 5; i++)
s3c_gpio_setpull(S5PC11X_GPJ1(i), S3C_GPIO_PULL_NONE);
/* drive strength to max */
writel(0xc0, S5PC11X_VA_GPIO + 0x10c);
writel(0x300, S5PC11X_VA_GPIO + 0x26c);
}
.label = "GPD1",
},
},
{
.base = S5PC11X_GPE0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC11X_GPE0(0),
.ngpio = S5PC11X_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.base = S5PC11X_GPE1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC11X_GPE1(0),
.ngpio = S5PC11X_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.base = S5PC11X_GPF0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PC11X_GPF0(0),
.ngpio = S5PC11X_GPIO_F0_NR,
.label = "GPF0",
},
}, {
.base = S5PC11X_GPF1_BASE,
.config = &gpio_cfg,
.chip = {