void S9xMainLoop(void)
{
int i;
for (;;)
{
for (i=0;i<32;i++) render_snescast();
if (CPU.NMILine)
{
if (Timings.NMITriggerPos <= CPU.Cycles)
{
CPU.NMILine = FALSE;
Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
S9xOpcode_NMI();
}
}
if (CPU.IRQTransition || CPU.IRQExternal)
{
if (CPU.IRQPending)
CPU.IRQPending--;
else
{
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
CPU.IRQTransition = FALSE;
CPU.IRQPending = Timings.IRQPendCount;
if (!CheckFlag(IRQ))
S9xOpcode_IRQ();
}
}
#ifdef DEBUGGER
if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
{
for (int Break = 0; Break != 6; Break++)
{
if (S9xBreakpoint[Break].Enabled &&
S9xBreakpoint[Break].Bank == Registers.PB &&
S9xBreakpoint[Break].Address == Registers.PCw)
{
if (S9xBreakpoint[Break].Enabled == 2)
S9xBreakpoint[Break].Enabled = TRUE;
else
CPU.Flags |= DEBUG_MODE_FLAG;
}
}
}
if (CPU.Flags & DEBUG_MODE_FLAG)
break;
if (CPU.Flags & TRACE_FLAG)
S9xTrace();
if (CPU.Flags & SINGLE_STEP_FLAG)
{
CPU.Flags &= ~SINGLE_STEP_FLAG;
CPU.Flags |= DEBUG_MODE_FLAG;
}
#endif
if (CPU.Flags & SCAN_KEYS_FLAG)
break;
register uint8 Op;
register struct SOpcodes *Opcodes;
if (CPU.PCBase)
{
Op = CPU.PCBase[Registers.PCw];
CPU.PrevCycles = CPU.Cycles;
CPU.Cycles += CPU.MemSpeed;
S9xCheckInterrupts();
Opcodes = ICPU.S9xOpcodes;
}
else
{
Op = S9xGetByte(Registers.PBPC);
OpenBus = Op;
Opcodes = S9xOpcodesSlow;
}
if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
{
uint8 *oldPCBase = CPU.PCBase;
CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
Opcodes = S9xOpcodesSlow;
}
Registers.PCw++;
(*Opcodes[Op].S9xOpcode)();
if (Settings.SA1)
S9xSA1MainLoop();
}
S9xPackStatus();
if (CPU.Flags & SCAN_KEYS_FLAG)
{
#ifdef DEBUGGER
if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
#endif
S9xSyncSpeed();
CPU.Flags &= ~SCAN_KEYS_FLAG;
}
}
void S9xMainLoop (void)
{
for (;;)
{
if (CPU.Flags)
{
if (CPU.Flags & NMI_FLAG)
{
if (Timings.NMITriggerPos <= CPU.Cycles)
{
CPU.Flags &= ~NMI_FLAG;
Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
S9xOpcode_NMI();
}
}
#ifdef DEBUGGER
if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
{
for (int Break = 0; Break != 6; Break++)
{
if (S9xBreakpoint[Break].Enabled &&
S9xBreakpoint[Break].Bank == Registers.PB &&
S9xBreakpoint[Break].Address == Registers.PCw)
{
if (S9xBreakpoint[Break].Enabled == 2)
S9xBreakpoint[Break].Enabled = TRUE;
else
CPU.Flags |= DEBUG_MODE_FLAG;
}
}
}
#endif
if (CPU.Flags & IRQ_FLAG)
{
if (CPU.IRQPending)
// FIXME: In case of IRQ during WRAM refresh
CPU.IRQPending--;
else
{
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
if (CPU.IRQActive && !Settings.DisableIRQ)
{
if (!CheckFlag(IRQ))
// in IRQ handler $4211 is supposed to be read, so IRQ_FLAG should be cleared.
S9xOpcode_IRQ();
}
else
CPU.Flags &= ~IRQ_FLAG;
}
}
if (CPU.Flags & SCAN_KEYS_FLAG)
break;
#ifdef DEBUGGER
if (CPU.Flags & DEBUG_MODE_FLAG)
break;
if (CPU.Flags & TRACE_FLAG)
S9xTrace();
if (CPU.Flags & SINGLE_STEP_FLAG)
{
CPU.Flags &= ~SINGLE_STEP_FLAG;
CPU.Flags |= DEBUG_MODE_FLAG;
}
#endif
}
#ifdef CPU_SHUTDOWN
CPU.PBPCAtOpcodeStart = Registers.PBPC;
#endif
register uint8 Op;
register struct SOpcodes *Opcodes;
CPU.PrevCycles = CPU.Cycles;
if (CPU.PCBase)
{
Op = CPU.PCBase[Registers.PCw];
CPU.Cycles += CPU.MemSpeed;
Opcodes = ICPU.S9xOpcodes;
}
else
{
Op = S9xGetByte(Registers.PBPC);
OpenBus = Op;
Opcodes = S9xOpcodesSlow;
}
if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
{
uint8 *oldPCBase = CPU.PCBase;
CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
Opcodes = S9xOpcodesSlow;
}
Registers.PCw++;
(*Opcodes[Op].S9xOpcode)();
if (SA1.Executing)
S9xSA1MainLoop();
#if (S9X_ACCURACY_LEVEL <= 2)
while (CPU.Cycles >= CPU.NextEvent)
S9xDoHEventProcessing();
#endif
}
S9xPackStatus();
if (CPU.Flags & SCAN_KEYS_FLAG)
{
#ifdef DEBUGGER
if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
#endif
S9xSyncSpeed();
CPU.Flags &= ~SCAN_KEYS_FLAG;
}
}
void S9xMainLoop (void)
{
#define CHECK_FOR_IRQ_CHANGE() \
if (Timings.IRQFlagChanging) \
{ \
if (Timings.IRQFlagChanging & IRQ_TRIGGER_NMI) \
{ \
CPU.NMIPending = TRUE; \
Timings.NMITriggerPos = CPU.Cycles + 6; \
} \
if (Timings.IRQFlagChanging & IRQ_CLEAR_FLAG) \
ClearIRQ(); \
else if (Timings.IRQFlagChanging & IRQ_SET_FLAG) \
SetIRQ(); \
Timings.IRQFlagChanging = IRQ_NONE; \
}
if (CPU.Flags & SCAN_KEYS_FLAG)
{
CPU.Flags &= ~SCAN_KEYS_FLAG;
S9xMovieUpdate();
}
for (;;)
{
if (CPU.NMIPending)
{
#ifdef DEBUGGER
if (Settings.TraceHCEvent)
S9xTraceFormattedMessage ("Comparing %d to %d\n", Timings.NMITriggerPos, CPU.Cycles);
#endif
if (Timings.NMITriggerPos <= CPU.Cycles)
{
CPU.NMIPending = FALSE;
Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
while (CPU.Cycles >= CPU.NextEvent)
S9xDoHEventProcessing();
}
CHECK_FOR_IRQ_CHANGE();
S9xOpcode_NMI();
}
}
if (CPU.Cycles >= Timings.NextIRQTimer)
{
#ifdef DEBUGGER
S9xTraceMessage ("Timer triggered\n");
#endif
S9xUpdateIRQPositions(false);
CPU.IRQLine = TRUE;
}
if (CPU.IRQLine || CPU.IRQExternal)
{
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
CPU.Cycles += TWO_CYCLES + ONE_DOT_CYCLE / 2;
while (CPU.Cycles >= CPU.NextEvent)
S9xDoHEventProcessing();
}
if (!CheckFlag(IRQ))
{
/* The flag pushed onto the stack is the new value */
CHECK_FOR_IRQ_CHANGE();
S9xOpcode_IRQ();
}
}
/* Change IRQ flag for instructions that set it only on last cycle */
CHECK_FOR_IRQ_CHANGE();
#ifdef DEBUGGER
if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
{
for (int Break = 0; Break != 6; Break++)
{
if (S9xBreakpoint[Break].Enabled &&
S9xBreakpoint[Break].Bank == Registers.PB &&
S9xBreakpoint[Break].Address == Registers.PCw)
{
if (S9xBreakpoint[Break].Enabled == 2)
S9xBreakpoint[Break].Enabled = TRUE;
else
CPU.Flags |= DEBUG_MODE_FLAG;
}
}
}
if (CPU.Flags & DEBUG_MODE_FLAG)
break;
if (CPU.Flags & TRACE_FLAG)
S9xTrace();
if (CPU.Flags & SINGLE_STEP_FLAG)
{
CPU.Flags &= ~SINGLE_STEP_FLAG;
CPU.Flags |= DEBUG_MODE_FLAG;
}
#endif
if (CPU.Flags & SCAN_KEYS_FLAG)
{
#ifdef DEBUGGER
if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
#endif
{
S9xSyncSpeed();
}
break;
}
uint8 Op;
struct SOpcodes *Opcodes;
if (CPU.PCBase)
{
Op = CPU.PCBase[Registers.PCw];
CPU.Cycles += CPU.MemSpeed;
Opcodes = ICPU.S9xOpcodes;
}
else
{
Op = S9xGetByte(Registers.PBPC);
OpenBus = Op;
Opcodes = S9xOpcodesSlow;
}
if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
{
uint8 *oldPCBase = CPU.PCBase;
CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
Opcodes = S9xOpcodesSlow;
}
Registers.PCw++;
(*Opcodes[Op].S9xOpcode)();
if (Settings.SA1)
S9xSA1MainLoop();
}
S9xPackStatus();
}
bool8 S9xDoDMA (uint8 Channel)
{
CPU.InDMA = TRUE;
CPU.InDMAorHDMA = TRUE;
CPU.CurrentDMAorHDMAChannel = Channel;
SDMA *d = &DMA[Channel];
// Check invalid DMA first
if ((d->ABank == 0x7E || d->ABank == 0x7F) && d->BAddress == 0x80 && !d->ReverseTransfer)
{
// Attempting a DMA from WRAM to $2180 will not work, WRAM will not be written.
// Attempting a DMA from $2180 to WRAM will similarly not work,
// the value written is (initially) the OpenBus value.
// In either case, the address in $2181-3 is not incremented.
// Does an invalid DMA actually take time?
// I'd say yes, since 'invalid' is probably just the WRAM chip
// not being able to read and write itself at the same time
// And no, PPU.WRAM should not be updated.
int32 c = d->TransferBytes;
// Writing $0000 to $43x5 actually results in a transfer of $10000 bytes, not 0.
if (c == 0)
c = 0x10000;
// 8 cycles per channel
ADD_CYCLES(SLOW_ONE_CYCLE);
// 8 cycles per byte
while (c)
{
d->TransferBytes--;
d->AAddress++;
c--;
if (!addCyclesInDMA(Channel))
{
CPU.InDMA = FALSE;
CPU.InDMAorHDMA = FALSE;
CPU.CurrentDMAorHDMAChannel = -1;
return (FALSE);
}
}
#ifdef DEBUGGER
if (Settings.TraceDMA)
{
sprintf(String, "DMA[%d]: WRAM Bank:%02X->$2180", Channel, d->ABank);
S9xMessage(S9X_TRACE, S9X_DMA_TRACE, String);
}
#endif
CPU.InDMA = FALSE;
CPU.InDMAorHDMA = FALSE;
CPU.CurrentDMAorHDMAChannel = -1;
return (TRUE);
}
// Prepare for accessing $2118-2119
switch (d->BAddress)
{
case 0x18:
case 0x19:
if (IPPU.RenderThisFrame)
FLUSH_REDRAW();
break;
}
int32 inc = d->AAddressFixed ? 0 : (!d->AAddressDecrement ? 1 : -1);
int32 count = d->TransferBytes;
// Writing $0000 to $43x5 actually results in a transfer of $10000 bytes, not 0.
if (count == 0)
count = 0x10000;
// Prepare for custom chip DMA
// S-DD1
uint8 *in_sdd1_dma = NULL;
if (Settings.SDD1)
{
if (d->AAddressFixed && Memory.FillRAM[0x4801] > 0)
{
// XXX: Should probably verify that we're DMAing from ROM?
// And somewhere we should make sure we're not running across a mapping boundary too.
// Hacky support for pre-decompressed S-DD1 data
inc = !d->AAddressDecrement ? 1 : -1;
uint8 *in_ptr = S9xGetBasePointer(((d->ABank << 16) | d->AAddress));
if (in_ptr)
{
in_ptr += d->AAddress;
SDD1_decompress(sdd1_decode_buffer, in_ptr, d->TransferBytes);
}
#ifdef DEBUGGER
else
{
sprintf(String, "S-DD1: DMA from non-block address $%02X:%04X", d->ABank, d->AAddress);
S9xMessage(S9X_WARNING, S9X_DMA_TRACE, String);
}
#endif
in_sdd1_dma = sdd1_decode_buffer;
}
Memory.FillRAM[0x4801] = 0;
}
// SPC7110
uint8 *spc7110_dma = NULL;
if (Settings.SPC7110)
{
if (d->AAddress == 0x4800 || d->ABank == 0x50)
{
spc7110_dma = new uint8[d->TransferBytes];
for (int i = 0; i < d->TransferBytes; i++)
spc7110_dma[i] = s7emu.decomp.read();
int32 icount = s7emu.r4809 | (s7emu.r480a << 8);
icount -= d->TransferBytes;
s7emu.r4809 = icount & 0x00ff;
s7emu.r480a = (icount & 0xff00) >> 8;
inc = 1;
d->AAddress -= count;
}
}
void S9xMainLoop (void)
{
static int loop_times=0;
int loops2=0;
//printf("Enter S9xMainLoop %d %x\n", loop_times, Registers.PCw);
for (;;)
{
loops2++;
//printf("S9xMainLoop %d for loop %d flags=%d\n", loop_times, loops2, CPU.Flags);
if (CPU.NMILine)
{
//printf("case 1\n");
if (Timings.NMITriggerPos <= CPU.Cycles)
{
CPU.NMILine = FALSE;
Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
S9xOpcode_NMI();
}
}
if (CPU.IRQTransition || CPU.IRQExternal)
{
//printf("case 2\n");
if (CPU.IRQPending)
CPU.IRQPending--;
else
{
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
CPU.IRQTransition = FALSE;
CPU.IRQPending = Timings.IRQPendCount;
if (!CheckFlag(IRQ))
S9xOpcode_IRQ();
}
}
#ifdef DEBUGGER
if ((CPU.Flags & BREAK_FLAG) && !(CPU.Flags & SINGLE_STEP_FLAG))
{
for (int Break = 0; Break != 6; Break++)
{
if (S9xBreakpoint[Break].Enabled &&
S9xBreakpoint[Break].Bank == Registers.PB &&
S9xBreakpoint[Break].Address == Registers.PCw)
{
if (S9xBreakpoint[Break].Enabled == 2)
S9xBreakpoint[Break].Enabled = TRUE;
else
CPU.Flags |= DEBUG_MODE_FLAG;
}
}
}
if (CPU.Flags & DEBUG_MODE_FLAG)
break;
if (CPU.Flags & TRACE_FLAG)
S9xTrace();
if (CPU.Flags & SINGLE_STEP_FLAG)
{
CPU.Flags &= ~SINGLE_STEP_FLAG;
CPU.Flags |= DEBUG_MODE_FLAG;
}
#endif
if (CPU.Flags & SCAN_KEYS_FLAG)
break;
register uint8 Op;
register Opcode *Opcodes;
if (CPU.PCBase)
{
Op = CPU.PCBase[Registers.PCw];
CPU.PrevCycles = CPU.Cycles;
CPU.Cycles += CPU.MemSpeed;
S9xCheckInterrupts();
Opcodes = ICPU.S9xOpcodes;
//printf("case 3 %x %x %d %d\n", Registers.PCw, Op, CPU.PrevCycles, CPU.Cycles);
}
else
{
//printf("case 4\n");
Op = S9xGetByte(Registers.PBPC);
OpenBus = Op;
Opcodes = S9xOpcodesSlow;
}
if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
{
uint8 *oldPCBase = CPU.PCBase;
//printf("case 5\n");
CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
Opcodes = S9xOpcodesSlow;
}
//printf("case 3.1 %d\n", CPU.Cycles);
Registers.PCw++;
Opcodes[Op]();
//printf("case 3.2 %d\n", CPU.Cycles);
if (Settings.SA1){
//printf("case 6\n");
S9xSA1MainLoop();
}
}
S9xPackStatus();
if (CPU.Flags & SCAN_KEYS_FLAG)
{
//printf("case 7\n");
#ifdef DEBUGGER
if (!(CPU.Flags & FRAME_ADVANCE_FLAG))
#endif
S9xSyncSpeed();
CPU.Flags &= ~SCAN_KEYS_FLAG;
}
//printf("Exit S9xMainLoop %d loops2=%d\n", loop_times++, loops2);
}
void S9xMainLoop (void)
{
do
{
register uint8 Op;
register struct SOpcodes *Opcodes;
/* Speedhack - skip idle loop if exists. */
if (idle_loop_elimination_enable &&
(Registers.PBPC == idle_loop_target_pc) && (CPU.Cycles < CPU.NextEvent))
CPU.Cycles = CPU.NextEvent;
if (CPU.Flags)
{
if (CPU.Flags & NMI_FLAG)
{
if (Timings.NMITriggerPos <= CPU.Cycles)
{
CPU.Flags &= ~NMI_FLAG;
Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
S9xOpcode_NMI();
}
}
if (CPU.Flags & IRQ_FLAG)
{
if (CPU.IRQPending)
CPU.IRQPending--; /* FIXME: In case of IRQ during WRAM refresh */
else
{
if (CPU.WaitingForInterrupt)
{
CPU.WaitingForInterrupt = FALSE;
Registers.PCw++;
}
if (CPU.IRQActive)
{
/* in IRQ handler $4211 is supposed to be read, so IRQ_FLAG should be cleared. */
if (!CheckFlag(IRQ))
S9xOpcode_IRQ();
}
else
CPU.Flags &= ~IRQ_FLAG;
}
}
if (CPU.Flags & SCAN_KEYS_FLAG)
break;
}
Opcodes = S9xOpcodesSlow;
CPU.PrevCycles = CPU.Cycles;
if (CPU.PCBase)
{
Op = CPU.PCBase[Registers.PCw];
CPU.Cycles += CPU.MemSpeed;
Opcodes = ICPU.S9xOpcodes;
}
else
{
Op = S9xGetByte(Registers.PBPC);
OpenBus = Op;
}
if ((Registers.PCw & MEMMAP_MASK) + ICPU.S9xOpLengths[Op] >= MEMMAP_BLOCK_SIZE)
{
uint8 *oldPCBase = CPU.PCBase;
CPU.PCBase = S9xGetBasePointer(ICPU.ShiftedPB + ((uint16) (Registers.PCw + 4)));
if (oldPCBase != CPU.PCBase || (Registers.PCw & ~MEMMAP_MASK) == (0xffff & ~MEMMAP_MASK))
Opcodes = S9xOpcodesSlow;
}
Registers.PCw++;
(*Opcodes[Op].S9xOpcode)();
if (Settings.SA1)
S9xSA1MainLoop();
#if (S9X_ACCURACY_LEVEL <= 2)
while (CPU.Cycles >= CPU.NextEvent)
S9xDoHEventProcessing();
#endif
}while(1);
S9xPackStatus();
if (CPU.Flags & SCAN_KEYS_FLAG)
{
CPU.Flags &= ~SCAN_KEYS_FLAG;
}
}
