static int s2m_set_voltage_sel_regmap_rev1(struct regulator_dev *rdev, unsigned sel)
{
int ret;
struct s2mps13_info *s2mps13 = rdev_get_drvdata(rdev);
int reg_id = rdev_get_id(rdev);
/* If dvs_en = 0, dvs_pin = 1, occur BUG_ON */
if (reg_id == S2MPS13_BUCK6 && SEC_PMIC_REV(s2mps13->iodev) > 0x02
&& !s2mps13->dvs_en && gpio_is_valid(s2mps13->dvs_pin)) {
BUG_ON(gpio_get_value(s2mps13->dvs_pin));
}
ret = regmap_write(rdev->regmap, rdev->desc->vsel_reg, sel);
if (ret < 0)
goto out;
if (rdev->desc->apply_bit)
ret = regmap_update_bits(rdev->regmap, rdev->desc->apply_reg,
rdev->desc->apply_bit,
rdev->desc->apply_bit);
return ret;
out :
pr_warn("%s: failed to set voltage_sel_regmap\n", rdev->desc->name);
return ret;
}
static int s2m_enable(struct regulator_dev *rdev)
{
struct s2mps13_info *s2mps13 = rdev_get_drvdata(rdev);
int reg_id = rdev_get_id(rdev);
/* disregard BUCK6 enable */
if (reg_id == S2MPS13_BUCK6 && SEC_PMIC_REV(s2mps13->iodev) > 0x02
&& s2mps13->g3d_en && gpio_is_valid(s2mps13->g3d_pin)) {
gpio_set_value(s2mps13->g3d_pin, 1);
return 0;
}
return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
rdev->desc->enable_mask,
s2mps13->opmode[rdev_get_id(rdev)]);
}
static int s2m_disable_regmap(struct regulator_dev *rdev)
{
struct s2mps13_info *s2mps13 = rdev_get_drvdata(rdev);
int reg_id = rdev_get_id(rdev);
unsigned int val;
/* disregard BUCK6 disable */
if (reg_id == S2MPS13_BUCK6 && SEC_PMIC_REV(s2mps13->iodev) > 0x02
&& s2mps13->g3d_en && gpio_is_valid(s2mps13->g3d_pin)) {
gpio_set_value(s2mps13->g3d_pin, 0);
return 0;
}
if (rdev->desc->enable_is_inverted)
val = rdev->desc->enable_mask;
else
val = 0;
return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
rdev->desc->enable_mask, val);
}
int s2m_get_voltage_sel_regmap(struct regulator_dev *rdev)
{
struct s2mps13_info *s2mps13 = rdev_get_drvdata(rdev);
int ret, reg_id = rdev_get_id(rdev);
unsigned int val;
/* if dvs pin set high, get the voltage on the diffrent register. */
if (reg_id == S2MPS13_BUCK6 && SEC_PMIC_REV(s2mps13->iodev) > 0x02
&& s2mps13->dvs_en && gpio_get_value(s2mps13->dvs_pin)) {
ret = regmap_read(rdev->regmap, S2MPS13_REG_B6CTRL3, &val);
if (ret != 0)
return ret;
} else {
ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val);
if (ret != 0)
return ret;
}
val &= rdev->desc->vsel_mask;
val >>= ffs(rdev->desc->vsel_mask) - 1;
return val;
}
static int s2m_is_enabled_regmap(struct regulator_dev *rdev)
{
struct s2mps13_info *s2mps13 = rdev_get_drvdata(rdev);
int ret, reg_id = rdev_get_id(rdev);
unsigned int val;
/* BUCK6 is controlled by g3d gpio */
if (reg_id == S2MPS13_BUCK6 && SEC_PMIC_REV(s2mps13->iodev) > 0x02
&& s2mps13->g3d_en && gpio_is_valid(s2mps13->g3d_pin)) {
if (gpio_get_value(s2mps13->g3d_pin))
return 1;
else
return 0;
} else {
ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
if (ret != 0)
return ret;
}
if (rdev->desc->enable_is_inverted)
return (val & rdev->desc->enable_mask) == 0;
else
return (val & rdev->desc->enable_mask) != 0;
}
static int s2mps13_pmic_probe(struct platform_device *pdev)
{
struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
struct sec_platform_data *pdata = iodev->pdata;
struct regulator_config config = { };
struct s2mps13_info *s2mps13;
int i, ret;
unsigned int s2mps13_desc_type;
ret = sec_reg_read(iodev, S2MPS13_REG_ID, &iodev->rev_num);
if (ret < 0)
return ret;
s2mps13_desc_type = SEC_PMIC_REV(iodev) ? S2MPS13_DESC_TYPE1 : S2MPS13_DESC_TYPE0;
if (iodev->dev->of_node) {
ret = s2mps13_pmic_dt_parse_pdata(iodev, pdata);
if (ret)
return ret;
}
if (!pdata) {
dev_err(pdev->dev.parent, "Platform data not supplied\n");
return -ENODEV;
}
s2mps13 = devm_kzalloc(&pdev->dev, sizeof(struct s2mps13_info),
GFP_KERNEL);
if (!s2mps13)
return -ENOMEM;
s2mps13->dvs_en = pdata->dvs_en;
s2mps13->g3d_en = pdata->g3d_en;
s2mps13->iodev = iodev;
static_info = s2mps13;
if (SEC_PMIC_REV(iodev) > 0x02 && gpio_is_valid(pdata->dvs_pin)) {
if (!pdata->dvs_en) {
/* Off DVS Control GPIO */
ret = devm_gpio_request(&pdev->dev, pdata->dvs_pin,
"S2MPS13 DVS_PIN");
if (ret < 0)
return ret;
gpio_direction_output(pdata->dvs_pin, 0);
} else {
/* Set DVS Regulator Voltage */
ret = sec_reg_write(iodev, S2MPS13_REG_B6CTRL3, 0x28);
if (ret < 0)
return ret;
if (!gpio_is_valid(pdata->dvs_pin)) {
dev_err(&pdev->dev, "dvs_pin GPIO NOT VALID\n");
return -EINVAL;
}
}
s2mps13->dvs_pin = pdata->dvs_pin;
}
platform_set_drvdata(pdev, s2mps13);
for (i = 0; i < pdata->num_regulators; i++) {
int id = pdata->regulators[i].id;
config.dev = &pdev->dev;
config.regmap = iodev->regmap;
config.init_data = pdata->regulators[i].initdata;
config.driver_data = s2mps13;
config.of_node = pdata->regulators[i].reg_node;
s2mps13->opmode[id] = regulators[s2mps13_desc_type][id].enable_mask;
s2mps13->rdev[i] = regulator_register(
®ulators[s2mps13_desc_type][id], &config);
if (IS_ERR(s2mps13->rdev[i])) {
ret = PTR_ERR(s2mps13->rdev[i]);
dev_err(&pdev->dev, "regulator init failed for %d\n",
i);
s2mps13->rdev[i] = NULL;
goto err;
}
}
if (pdata->g3d_en
&& SEC_PMIC_REV(iodev) > 0x02 && gpio_is_valid(pdata->g3d_pin)) {
ret = devm_gpio_request(&pdev->dev, pdata->g3d_pin,
"S2MPS13 G3D_PIN");
if (pdata->g3d_en) {
gpio_direction_output(pdata->g3d_pin, 1);
udelay(128);
ret = sec_reg_update(iodev, S2MPS13_REG_B6CTRL1, 0x00, 0xC0);
ret = sec_reg_update(iodev, S2MPS13_REG_LDO_DVS3, 0x02, 0x02);
} else
gpio_direction_output(pdata->g3d_pin, 0);
s2mps13->g3d_pin = pdata->g3d_pin;
}
/* PMIC AVP(Adaptive Voltage Positioning) Configuration */
if (pdata->ap_buck_avp_en) {
sec_reg_write(iodev, 0x91, 0x4F); /* Buck4 AVP level 11mV/A */
sec_reg_write(iodev, 0x99, 0x4D); /* Buck6 AVP level 7mV/A */
sec_reg_update(iodev, S2MPS13_REG_B4CTRL1, 0x02, 0x02); /* Buck4 AVP On */
sec_reg_update(iodev, S2MPS13_REG_B6CTRL1, 0x02, 0x02); /* Buck6 AVP On */
}
if (pdata->sub_buck_avp_en) {
sec_reg_write(iodev, 0xBA, 0x4C); /* Buck8 AVP level 90mV/A */
sec_reg_write(iodev, 0xBB, 0x6A); /* Buck9 AVP level 115mV/A */
sec_reg_write(iodev, 0xB1, 0x0A); /* Buck8 AVP amp offset code */
sec_reg_write(iodev, 0xB5, 0x2A); /* Buck9 AVP amp offset code */
sec_reg_update(iodev, S2MPS13_REG_B8CTRL1, 0x02, 0x02); /* Buck8 AVP On */
sec_reg_update(iodev, S2MPS13_REG_B9CTRL1, 0x02, 0x02); /* Buck9 AVP On */
}
return 0;
err:
for (i = 0; i < S2MPS13_REGULATOR_MAX; i++)
regulator_unregister(s2mps13->rdev[i]);
return ret;
}
static int s2mps13_pmic_dt_parse_pdata(struct sec_pmic_dev *iodev,
struct sec_platform_data *pdata)
{
struct device_node *pmic_np, *regulators_np, *reg_np;
struct sec_regulator_data *rdata;
unsigned int i, s2mps13_desc_type;
int ret;
u32 val;
pmic_np = iodev->dev->of_node;
if (!pmic_np) {
dev_err(iodev->dev, "could not find pmic sub-node\n");
return -ENODEV;
}
/* If pmic revision number over 0x02, get 3 gpio values */
if (SEC_PMIC_REV(iodev) > 0x02) {
if (of_gpio_count(pmic_np) < 3) {
dev_err(iodev->dev, "could not find pmic gpios\n");
return -EINVAL;
}
pdata->smpl_warn = of_get_gpio(pmic_np, 0);
pdata->g3d_pin = of_get_gpio(pmic_np, 1);
pdata->dvs_pin = of_get_gpio(pmic_np, 2);
ret = of_property_read_u32(pmic_np, "g3d_en", &val);
if (ret)
return -EINVAL;
pdata->g3d_en = !!val;
ret = of_property_read_u32(pmic_np, "dvs_en", &val);
if (ret)
return -EINVAL;
pdata->dvs_en = !!val;
ret = of_property_read_u32(pmic_np, "smpl_warn_en", &val);
if (ret)
return -EINVAL;
pdata->smpl_warn_en = !!val;
} else {
dev_err(iodev->dev, "cannot control g3d_en & dvs_en\n");
}
pdata->ap_buck_avp_en = false;
pdata->sub_buck_avp_en = false;
if (of_find_property(pmic_np, "ap-buck-avp-en", NULL))
pdata->ap_buck_avp_en = true;
if (of_find_property(pmic_np, "sub-buck-avp-en", NULL))
pdata->sub_buck_avp_en = true;
regulators_np = of_find_node_by_name(pmic_np, "regulators");
if (!regulators_np) {
dev_err(iodev->dev, "could not find regulators sub-node\n");
return -EINVAL;
}
/* count the number of regulators to be supported in pmic */
pdata->num_regulators = 0;
for_each_child_of_node(regulators_np, reg_np) {
pdata->num_regulators++;
}
rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) *
pdata->num_regulators, GFP_KERNEL);
if (!rdata) {
dev_err(iodev->dev,
"could not allocate memory for regulator data\n");
return -ENOMEM;
}
pdata->regulators = rdata;
s2mps13_desc_type = SEC_PMIC_REV(iodev) ? S2MPS13_DESC_TYPE1 : S2MPS13_DESC_TYPE0;
for_each_child_of_node(regulators_np, reg_np) {
for (i = 0; i < ARRAY_SIZE(regulators[s2mps13_desc_type]); i++)
if (!of_node_cmp(reg_np->name,
regulators[s2mps13_desc_type][i].name))
break;
if (i == ARRAY_SIZE(regulators[s2mps13_desc_type])) {
dev_warn(iodev->dev,
"don't know how to configure regulator %s\n",
reg_np->name);
continue;
}
rdata->id = i;
rdata->initdata = of_get_regulator_init_data(
iodev->dev, reg_np);
rdata->reg_node = reg_np;
rdata++;
}
return 0;
}
static int s2mps16_pmic_probe(struct platform_device *pdev)
{
struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
struct sec_platform_data *pdata = iodev->pdata;
struct regulator_config config = { };
struct s2mps16_info *s2mps16;
int i, ret, delta_sel;
unsigned int temp;
unsigned int s2mps16_desc_type;
unsigned int buck2_temp = 0;
ret = sec_reg_read(iodev, S2MPS16_REG_ID, &SEC_PMIC_REV(iodev));
if (ret < 0)
return ret;
s2mps16_desc_type = S2MPS16_DESC_TYPE0;
if (iodev->dev->of_node) {
ret = s2mps16_pmic_dt_parse_pdata(iodev, pdata);
if (ret)
return ret;
}
if (!pdata) {
dev_err(pdev->dev.parent, "Platform data not supplied\n");
return -ENODEV;
}
s2mps16 = devm_kzalloc(&pdev->dev, sizeof(struct s2mps16_info),
GFP_KERNEL);
if (!s2mps16)
return -ENOMEM;
s2mps16->desc_type = s2mps16_desc_type;
s2mps16->iodev = iodev;
s2mps16->buck11_en = (const char *)of_find_property(iodev->dev->of_node,
"buck11_en", NULL);
mutex_init(&s2mps16->lock);
static_info = s2mps16;
s2mps16->dvs_en = pdata->dvs_en;
s2mps16->g3d_en = pdata->g3d_en;
s2mps16->cache_data = pdata->cache_data;
s2mps16->int_max = 0;
s2mps16->buck_dvs_on = pdata->buck_dvs_on;
if (s2mps16->buck_dvs_on)
dev_info(&pdev->dev, "Buck dvs mode enabled \n");
if (gpio_is_valid(pdata->dvs_pin)) {
ret = devm_gpio_request(&pdev->dev, pdata->dvs_pin,
"S2MPS16 DVS_PIN");
if (ret < 0)
return ret;
if (pdata->dvs_en) {
/* Set DVS Regulator Voltage 0x20 - 0.5 voltage */
ret = sec_reg_write(iodev, S2MPS16_REG_B6CTRL2, 0x20);
if (ret < 0)
return ret;
s2m_init_dvs();
s2mps16->dvs_pin = pdata->dvs_pin;
} else
dev_err(&pdev->dev, "g3d dvs is not enabled.\n");
}
platform_set_drvdata(pdev, s2mps16);
for (i = 0; i < pdata->num_regulators; i++) {
int id = pdata->regulators[i].id;
config.dev = &pdev->dev;
config.regmap = iodev->regmap;
config.init_data = pdata->regulators[i].initdata;
config.driver_data = s2mps16;
config.of_node = pdata->regulators[i].reg_node;
s2mps16->opmode[id] =
regulators[s2mps16_desc_type][id].enable_mask;
s2mps16->rdev[i] = regulator_register(
®ulators[s2mps16_desc_type][id], &config);
if (IS_ERR(s2mps16->rdev[i])) {
ret = PTR_ERR(s2mps16->rdev[i]);
dev_err(&pdev->dev, "regulator init failed for %d\n",
i);
s2mps16->rdev[i] = NULL;
goto err;
}
if ((id == S2MPS16_BUCK1 || id == S2MPS16_BUCK2
|| id == S2MPS16_BUCK3 || id == S2MPS16_LDO8)
&& s2mps16->buck_dvs_on) {
mutex_lock(&s2mps16->lock);
ret = s2m_set_ldo_dvs_control(s2mps16->rdev[i]);
if (ret < 0)
dev_err(&pdev->dev, "failed vth/delta init, id(%d)\n", id);
mutex_unlock(&s2mps16->lock);
}
}
s2mps16->num_regulators = pdata->num_regulators;
if (s2mps16->buck_dvs_on) {
delta_sel = 0;
if (s2mps16->buck2_dvs == 0)
delta_sel = 100000;
else if (s2mps16->buck2_dvs == 1)
delta_sel = 0;
else if (s2mps16->buck2_dvs == 2)
delta_sel = 75000;
else if (s2mps16->buck2_dvs == 3)
delta_sel = 50000;
else
delta_sel = 0;
delta_sel = delta_sel / S2MPS16_BUCK_STEP1;
/* Read BUCK2_OUT value */
ret = sec_reg_read(iodev, S2MPS16_REG_B2CTRL2, &temp);
if (ret < 0)
goto err;
buck2_temp = temp;
/* Check tar_volt+delta range (0x98 means 1250000uV) */
s2mps16->buck2_sync = (temp + delta_sel > 0x98) ? false : true;
if (!s2mps16->buck2_sync) {
/* Set BUCK2 output voltage 1150000uV */
ret = sec_reg_write(s2mps16->iodev, S2MPS16_REG_B2CTRL2, 0x88);
if (ret < 0)
goto err;
/* Disable buck2 dvs mode */
ret = sec_reg_update(s2mps16->iodev, S2MPS16_REG_LDO7_DVS,
0 << 2, 0x1 << 2);
if (ret < 0)
goto err;
/* Set buck previous target voltage */
ret = sec_reg_write(s2mps16->iodev, S2MPS16_REG_B2CTRL2, buck2_temp);
if (ret < 0)
goto err;
}
ret = sec_reg_read(iodev, S2MPS16_REG_LDO7_DVS, &temp);
if (ret < 0)
goto err;
ret = sec_reg_read(iodev, S2MPS16_REG_B4CTRL2, &s2mps16->buck4_sel);
if (ret < 0)
goto err;
ret = sec_reg_read(iodev, S2MPS16_REG_B5CTRL2, &s2mps16->buck5_sel);
if (ret < 0)
goto err;
dev_info(&pdev->dev, "S2MPS16_REG_LDO7_DVS : %8.x \n", temp);
dev_info(&pdev->dev, "S2MPS16_REG_B4CTRL2 : %8.x \n", s2mps16->buck4_sel);
dev_info(&pdev->dev, "S2MPS16_REG_B5CTRL2 : %8.x \n", s2mps16->buck5_sel);
s2mps16->int_max = s2m_get_max_int_voltage(s2mps16);
}
if (pdata->g3d_en) {
/* for buck6 gpio control, disable i2c control */
ret = sec_reg_update(iodev, S2MPS16_REG_B6CTRL1,
0x80, 0xC0);
if (ret) {
dev_err(&pdev->dev, "buck6 gpio control error\n");
goto err;
}
if (!s2mps16->buck11_en) {
ret = sec_reg_update(iodev, S2MPS16_REG_L11CTRL,
0x00, 0xC0);
if (ret) {
dev_err(&pdev->dev, "regulator sync enable error\n");
goto err;
}
} else {
/* for buck11 gpio control, disable i2c control */
ret = sec_reg_update(iodev, S2MPS16_REG_B11CTRL1,
0x80, 0xC0);
if (ret) {
dev_err(&pdev->dev, "buck11 gpio control error\n");
goto err;
}
}
}
if (pdata->smpl_warn_en) {
ret = sec_reg_update(iodev, S2MPS16_REG_CTRL2,
pdata->smpl_warn_vth, 0xe0);
if (ret) {
dev_err(&pdev->dev, "set smpl_warn configuration i2c write error\n");
goto err;
}
pr_info("%s: smpl_warn vth is 0x%x\n", __func__,
pdata->smpl_warn_vth);
ret = sec_reg_update(iodev, S2MPS16_REG_CTRL2,
pdata->smpl_warn_hys, 0x18);
if (ret) {
dev_err(&pdev->dev, "set smpl_warn configuration i2c write error\n");
goto err;
}
pr_info("%s: smpl_warn hysteresis is 0x%x\n", __func__,
pdata->smpl_warn_hys);
}
/* RTC Low jitter mode */
ret = sec_reg_update(iodev, S2MPS16_REG_RTC_BUF, 0x10, 0x10);
if (ret) {
dev_err(&pdev->dev, "set low jitter mode i2c write error\n");
goto err;
}
/* SELMIF set LDO2,4,5,6,8,9,12,13 controlled by PWREN_MIF */
ret = sec_reg_write(iodev, S2MPS16_REG_SELMIF, 0xFF);
if (ret) {
dev_err(&pdev->dev, "set selmif sel error\n");
goto err;
}
sec_reg_update(iodev, S2MPS16_REG_B4CTRL1, 0x00, 0x10);
ret = sec_reg_write(iodev, 0x9B, 0x10);
if (ret) {
dev_err(&pdev->dev, "BUCK8, BUCK9 DVS setting failed\n");
goto err;
}
/* On sequence Config for PWREN_MIF */
sec_reg_write(iodev, 0x70, 0xB4); /* seq. Buck2, Buck1 */
sec_reg_write(iodev, 0x71, 0x2C); /* seq. Buck4, Buck3 */
sec_reg_write(iodev, 0x72, 0xD4); /* seq. Buck6, Buck5 */
sec_reg_write(iodev, 0x73, 0x11); /* seq. Buck8, Buck7 */
sec_reg_write(iodev, 0x74, 0xE0); /* seq. Buck10, Buck9 */
if (s2mps16->buck11_en)
sec_reg_write(iodev, 0x75, 0x27); /* seq. BB, Buck11 */
else
sec_reg_write(iodev, 0x75, 0x20);
sec_reg_write(iodev, 0x76, 0x93); /* seq. LDO2, LDO1 */
sec_reg_write(iodev, 0x77, 0x60); /* Seq. LDO4, LDO3 */
sec_reg_write(iodev, 0x78, 0x87); /* seq. LDO6, LDO5 */
sec_reg_write(iodev, 0x79, pdata->ldo8_7_seq); /* Seq. LDO8, LDO7 */
sec_reg_write(iodev, 0x7A, pdata->ldo10_9_seq); /* Seq. LDO10, LDO9 */
if (s2mps16->buck11_en)
sec_reg_write(iodev, 0x7B, 0x50); /* Seq. LDO12, LDO11 */
else
sec_reg_write(iodev, 0x7B, 0x57);
sec_reg_write(iodev, 0x7C, 0x75); /* Seq. LDO14, LDO13 */
sec_reg_write(iodev, 0x7D, 0x98); /* Seq. LDO16, LDO15 */
sec_reg_write(iodev, 0x7E, 0x00); /* Seq. LDO18, LDO17 */
sec_reg_write(iodev, 0x7F, 0x00); /* Seq. LDO20, LDO19 */
sec_reg_write(iodev, 0x80, 0x21); /* Seq. LDO22, LDO21 */
sec_reg_write(iodev, 0x81, 0x3F); /* Seq. LDO24, LDO23 */
sec_reg_write(iodev, 0x82, 0x00); /* Seq. LDO26, LDO25 */
sec_reg_write(iodev, 0x83, 0x40); /* Seq. B1~B8*/
sec_reg_write(iodev, 0x84, 0x40); /* Seq. B9~B11, BB, LDO1~4 */
sec_reg_write(iodev, 0x85, 0x00); /* Seq. LDO5~12 */
sec_reg_write(iodev, 0x86, 0x0E); /* Seq. LDO13~20 */
sec_reg_write(iodev, 0x87, 0x00); /* Seq. LDO26~21 */
return 0;
err:
for (i = 0; i < S2MPS16_REGULATOR_MAX; i++)
regulator_unregister(s2mps16->rdev[i]);
return ret;
}
