static int sunxi_clk_disable_plllock(struct sunxi_clk_factors *factor)
{
volatile u32 reg;
switch (factor->lock_mode) {
case PLL_LOCK_NEW_MODE:
case PLL_LOCK_OLD_MODE: {
/* make sure pll new mode is disable */
reg = factor_readl(factor,factor->pll_lock_ctrl_reg);
reg = SET_BITS(factor->lock_en_bit, 1, reg, 0);
factor_writel(factor,reg, factor->pll_lock_ctrl_reg);
reg = factor_readl(factor, factor->pll_lock_ctrl_reg);
reg = SET_BITS(28, 1, reg, 0);
factor_writel(factor, reg, factor->pll_lock_ctrl_reg);
return 0;
}
case PLL_LOCK_NONE_MODE: {
return 0;
}
default: {
WARN(1, "invaid pll lock mode:%u\n", factor->lock_mode);
return -1;
}
}
}
/*************************************************************************
Author: Josiah Snarr
Date: April 9, 2015
spiInit initializes the SPI for 1MHz baud and no slave select
*************************************************************************/
void spiInit(void)
{
SPICR1 = SPICR1_SETUP;
SPIBR = SPIBR_SETUP;
SET_BITS(SPI_DDR, SPI_SS); //Set SS as manual output (GPIO)
SET_BITS(SPI_PORT, SPI_SS); //Initialize high
}
static void sunxi_clk_fators_disable(struct clk_hw *hw)
{
struct sunxi_clk_factors *factor = to_clk_factor(hw);
struct sunxi_clk_factors_config *config = factor->config;
unsigned long reg;
unsigned long flags = 0;
if(factor->flags & CLK_IGNORE_DISABLE)
return;
/* check if the pll disabled already */
reg = factor_readl(factor, factor->reg);
if(!GET_BITS(config->enshift, 1, reg))
return;
if(factor->lock)
spin_lock_irqsave(factor->lock, flags);
reg = factor_readl(factor, factor->reg);
if(config->sdmwidth)
reg = SET_BITS(config->sdmshift, config->sdmwidth, reg, 0);
/* update for pll_ddr register */
if(config->updshift)
reg = SET_BITS(config->updshift, 1, reg, 1);
/* disable pll */
reg = SET_BITS(config->enshift, 1, reg, 0);
factor_writel(factor,reg, factor->reg);
/* disable pll lock if needed */
sunxi_clk_disable_plllock(factor);
if(factor->lock)
spin_unlock_irqrestore(factor->lock, flags);
}
static int sunxi_clk_periph_set_parent(struct clk_hw *hw, u8 index)
{
unsigned long reg, flags = 0;
struct sunxi_clk_periph *periph = to_clk_periph(hw);
if(periph->flags & CLK_READONLY)
return 0;
if(!periph->mux.reg)
return 0;
if(periph->lock)
{
spin_lock_irqsave(periph->lock, flags);
reg = periph_readl(periph,periph->mux.reg);
reg = SET_BITS(periph->mux.shift, periph->mux.width, reg, index);
periph_writel(periph,reg, periph->mux.reg);
spin_unlock_irqrestore(periph->lock, flags);
}
else
{
reg = periph_readl(periph,periph->mux.reg);
reg = SET_BITS(periph->mux.shift, periph->mux.width, reg, index);
periph_writel(periph,reg, periph->mux.reg);
}
return 0;
}
static int __sunxi_clk_periph_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
{
struct sunxi_clk_periph *periph = to_clk_periph(hw);
struct sunxi_clk_periph_div *divider = &periph->divider;
int i,j,m_max;
int m=0,n=0;
unsigned long cur_rate=0,new_rate=0;
unsigned long cur_delta,new_delta;
u32 reg;
if(parent_rate == 4000000)
m_max =1;
else
m_max = 8;
for(i=0;i<m_max;i++)
for(j=0;j<8;j++)
{
new_rate = parent_rate/(ac100_m_factor[i]*ac100_n_factor[j]);
new_delta = (new_rate >rate)?(new_rate-rate):(rate-new_rate);
cur_delta = (cur_rate >rate)?(cur_rate-rate):(rate-cur_rate);
if(new_delta < cur_delta)
{
cur_rate = new_rate;
m =i;
n = j;
}
}
reg = periph_readl(periph,divider->reg);
if(divider->mwidth)
reg = SET_BITS(divider->mshift, divider->mwidth, reg, m);
if(divider->nwidth)
reg = SET_BITS(divider->nshift, divider->nwidth, reg, n);
periph_writel(periph,reg, divider->reg);
return 0;
}
static void rc32434_wdt_start(void)
{
u32 or, nand;
spin_lock(&rc32434_wdt_device.io_lock);
/* zero the counter before enabling */
writel(0, &wdt_reg->wtcount);
/* don't generate a non-maskable interrupt,
* do a warm reset instead */
nand = 1 << RC32434_ERR_WNE;
or = 1 << RC32434_ERR_WRE;
/* reset the ERRCS timeout bit in case it's set */
nand |= 1 << RC32434_ERR_WTO;
SET_BITS(wdt_reg->errcs, or, nand);
/* set the timeout (either default or based on module param) */
rc32434_wdt_set(timeout);
/* reset WTC timeout bit and enable WDT */
nand = 1 << RC32434_WTC_TO;
or = 1 << RC32434_WTC_EN;
SET_BITS(wdt_reg->wtc, or, nand);
spin_unlock(&rc32434_wdt_device.io_lock);
pr_info("Started watchdog timer\n");
}
bool ADC::init() {
//ADC reset
SET_BIT(* (VINTP)(ADC_MODULE + ADC_CR_OFFSET), 0);
//ADC Clock einstellen
prescalerRate = Configuration::ADCCLK / (Configuration::ADC_Internal_Clock * 2);
//prescalerRate darf nicht zu gross werden
if (prescalerRate > 255)
return false;
//Prescale Inhalt loeschen
CLEAR_BITS(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 0xFF << 8);
//prescalerRate in das Mode Register reinschreiben
SET_BITS(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), (prescalerRate & 0xFF) << 8);
//Startup time einstellen
startupTime = Configuration::ADCCLK / ((prescalerRate + 1) * 800000);
if (startupTime > 127)
return false;
//startup time Inhalt loeschen
CLEAR_BITS(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 0x7F << 16);
//neuen Inhalt reinschreiben
SET_BITS(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), (startupTime & 0x7F) << 16);
SET_BITS(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 0xF << 24);
//Hardware Trigger deaktivieren,
CLEAR_BIT(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 0);
//10-bit Konvertierung einstellen
CLEAR_BIT(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 4);
//normalen Modus waehlen, kein Sleep Mode
CLEAR_BIT(* (VINTP)(ADC_MODULE + ADC_MR_OFFSET), 5);
//eine Konvertierung starten
//SET_BIT ( *( VINTP ) ( ADC_MODULE + CR_OFFSET ), 1 );
return 1;
}
s32 de_top_clk_enable(u32 mod_id, u32 enable)
{
struct de_top_clk *top_clk;
u32 i;
for(i=0; i<(sizeof(de_top_clk_array)/sizeof(struct de_top_clk)); i++) {
if((de_top_clk_array[i].mod_id == mod_id) && (0 != top_base)) {
u32 reg_val;
top_clk = &de_top_clk_array[i];
/* bus clk */
reg_val = readl(top_base + top_clk->gate.bus_off);
reg_val = SET_BITS(top_clk->gate.bus_shift, 1, reg_val, 1);
writel(reg_val, top_base + top_clk->gate.bus_off);
/* module clk */
reg_val = readl(top_base + top_clk->gate.enable_off);
reg_val = SET_BITS(top_clk->gate.enable_shift, 1, reg_val, 1);
writel(reg_val, top_base + top_clk->gate.enable_off);
/* reset clk */
reg_val = readl(top_base + top_clk->gate.reset_off);
reg_val = SET_BITS(top_clk->gate.reset_shift, 1, reg_val, 1);
writel(reg_val, top_base + top_clk->gate.reset_off);
/* dram clk */
reg_val = readl(top_base + top_clk->gate.dram_off);
reg_val = SET_BITS(top_clk->gate.dram_shift, 1, reg_val, 1);
writel(reg_val, top_base + top_clk->gate.dram_off);
return 0;
}
}
return -1;
}
u32 de_pll_enable(__disp_clk_id_t clk_id, s32 bOnOff)
{
u32 i;
u32 count;
u32 reg_val;
count = sizeof(disp_clk_pll_tbl) / sizeof(clk_pll_para);
for(i = 0; i < count; i++)
{
if(disp_clk_pll_tbl[i].clk_id == clk_id)
{
reg_val = smc_readl(disp_clk_pll_tbl[i].pll_adr);
if(bOnOff)
{
pll_enable_count[i]++;
if(pll_enable_count[i] == 1)
{
reg_val = SET_BITS(disp_clk_pll_tbl[i].enable_shift, 1, reg_val, 1);
modify_cpu_source_ctrl();
smc_writel(reg_val, disp_clk_pll_tbl[i].pll_adr);
restore_cpu_source_ctrl();
if(disp_clk_pll_tbl[i].src_id)
{
de_pll_enable(disp_clk_pll_tbl[i].src_id, bOnOff);
}
}
__inf("enable pll %d\n", clk_id);
return 1;
}
else
{
if(pll_enable_count[i] == 0)
{
__wrn("pll %d is already disable\n", clk_id);
}
pll_enable_count[i]--;
if(pll_enable_count[i] == 0)
{
reg_val = SET_BITS(disp_clk_pll_tbl[i].enable_shift, 1, reg_val, 0);
modify_cpu_source_ctrl();
smc_writel(reg_val, disp_clk_pll_tbl[i].pll_adr);
restore_cpu_source_ctrl();
if(disp_clk_pll_tbl[i].src_id)
{
de_pll_enable(disp_clk_pll_tbl[i].src_id, bOnOff);
}
}
__inf("disable pll %d\n", clk_id);
return 1;
}
}
}
return 0;
}
static void clk_disable_pll_mipi(struct clk_hw *hw)
{
struct sunxi_clk_factors *factor = to_clk_factor(hw);
struct sunxi_clk_factors_config *config = factor->config;
unsigned long reg = readl(factor->reg);
if(config->sdmwidth)
reg = SET_BITS(config->sdmshift, config->sdmwidth, reg, 0);
reg = SET_BITS(config->enshift, 1, reg, 0);
reg &= ~(0x3 << 22);
writel(reg, factor->reg);
}
/*
* Enable a timer.
*
* @param timer - A timer module (e.g. TIMER_0)
* @param ab - Select timer A or timer B.
*/
void timer_enable(timer_module_t timer, timer_ab_t ab)
{
timer_registers_t *p_timer = timers[timer];
if (ab == TIMER_A)
{
SET_BITS(p_timer->CTRL, (1 << 0));
}
else
{
SET_BITS(p_timer->CTRL, (1 << 8));
}
}
static void sunxi_clk_fators_disable(struct clk_hw *hw)
{
struct sunxi_clk_factors *factor = to_clk_factor(hw);
struct sunxi_clk_factors_config *config = factor->config;
unsigned long reg = factor_readl(factor,factor->reg);
if(config->sdmwidth)
reg = SET_BITS(config->sdmshift, config->sdmwidth, reg, 0);
reg = SET_BITS(config->enshift, 1, reg, 0);
factor_writel(factor,reg, factor->reg);
}
int get_input(void)
{
int input = 0;
Uint8 *keys = SDL_GetKeyState(NULL);
if(keys[SDLK_RETURN])
input=SET_BITS(input,PRESS_ENTER);
if(keys[SDLK_ESCAPE])
input=SET_BITS(input,PRESS_ESC);
if(keys[SDLK_UP])
input=SET_BITS(input,PRESS_UP);
if(keys[SDLK_RIGHT])
input=SET_BITS(input,PRESS_RIGHT);
if(keys[SDLK_LEFT])
input=SET_BITS(input,PRESS_LEFT);
if(keys[SDLK_DOWN])
input=SET_BITS(input,PRESS_DOWN);
if(keys[SDLK_SPACE])
input=SET_BITS(input,PRESS_JUMP);
if(keys[SDLK_LCTRL])
input=SET_BITS(input,PRESS_ATTACK);
return input;
}
int get_input_keydown(int ks)
{
int input = 0;
switch(ks)
{
case SDLK_RETURN:
input=SET_BITS(input,PRESS_ENTER);
break;
case SDLK_ESCAPE:
input=SET_BITS(input,PRESS_ESC);
break;
case SDLK_UP:
input=SET_BITS(input,PRESS_UP);
break;
case SDLK_RIGHT:
input=SET_BITS(input,PRESS_RIGHT);
break;
case SDLK_LEFT:
input=SET_BITS(input,PRESS_LEFT);
break;
case SDLK_DOWN:
input=SET_BITS(input,PRESS_DOWN);
break;
case SDLK_SPACE:
input=SET_BITS(input,PRESS_JUMP);
break;
case SDLK_LCTRL:
input=SET_BITS(input,PRESS_ATTACK);
break;
default: break;
}
return input;
}
static int xge_refill_buffers(struct net_device *ndev, u32 nbuf)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct xge_desc_ring *ring = pdata->rx_ring;
const u8 slots = XGENE_ENET_NUM_DESC - 1;
struct device *dev = &pdata->pdev->dev;
struct xge_raw_desc *raw_desc;
u64 addr_lo, addr_hi;
u8 tail = ring->tail;
struct sk_buff *skb;
dma_addr_t dma_addr;
u16 len;
int i;
for (i = 0; i < nbuf; i++) {
raw_desc = &ring->raw_desc[tail];
len = XGENE_ENET_STD_MTU;
skb = netdev_alloc_skb(ndev, len);
if (unlikely(!skb))
return -ENOMEM;
dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
if (dma_mapping_error(dev, dma_addr)) {
netdev_err(ndev, "DMA mapping error\n");
dev_kfree_skb_any(skb);
return -EINVAL;
}
ring->pkt_info[tail].skb = skb;
ring->pkt_info[tail].dma_addr = dma_addr;
addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1));
addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1));
raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) |
SET_BITS(NEXT_DESC_ADDRH, addr_hi) |
SET_BITS(PKT_ADDRH,
upper_32_bits(dma_addr)));
dma_wmb();
raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) |
SET_BITS(E, 1));
tail = (tail + 1) & slots;
}
ring->tail = tail;
return 0;
}
static int sunxi_clk_fators_enable(struct clk_hw *hw)
{
struct sunxi_clk_factors *factor = to_clk_factor(hw);
struct sunxi_clk_factors_config *config = factor->config;
unsigned long reg = factor_readl(factor,factor->reg);
if(config->sdmwidth)
{
factor_writel(factor,config->sdmval, (void __iomem *)config->sdmpat);
reg = SET_BITS(config->sdmshift, config->sdmwidth, reg, 1);
}
reg = SET_BITS(config->enshift, 1, reg, 1);
factor_writel(factor,reg, factor->reg);
return 0;
}
static void xge_txc_poll(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *tx_ring;
struct xge_raw_desc *raw_desc;
dma_addr_t dma_addr;
struct sk_buff *skb;
void *pkt_buf;
u32 data;
u8 head;
tx_ring = pdata->tx_ring;
head = tx_ring->head;
data = xge_rd_csr(pdata, DMATXSTATUS);
if (!GET_BITS(TXPKTCOUNT, data))
return;
while (1) {
raw_desc = &tx_ring->raw_desc[head];
if (!is_tx_hw_done(raw_desc))
break;
dma_rmb();
skb = tx_ring->pkt_info[head].skb;
dma_addr = tx_ring->pkt_info[head].dma_addr;
pkt_buf = tx_ring->pkt_info[head].pkt_buf;
pdata->stats.tx_packets++;
pdata->stats.tx_bytes += skb->len;
dma_free_coherent(dev, XGENE_ENET_STD_MTU, pkt_buf, dma_addr);
dev_kfree_skb_any(skb);
/* clear pktstart address and pktsize */
raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
SET_BITS(PKT_SIZE, SLOT_EMPTY));
xge_wr_csr(pdata, DMATXSTATUS, 1);
head = (head + 1) & (XGENE_ENET_NUM_DESC - 1);
}
if (netif_queue_stopped(ndev))
netif_wake_queue(ndev);
tx_ring->head = head;
}
/*************************************************************************
Author: Josiah Snarr
Date: April 9, 2015
DACSend forms a header for data sent to the DAC, and sends the data with
the specified instruction (0 - LDAB, 1 - LDA, 2 - LDB)
*************************************************************************/
void DACSend(unsigned char dVal, unsigned char inst)
{
char lss; //Least significant set to send
char mss; //Most significant set to send
switch(inst) //Find command and form MSB side of header
{
case COM_LDA:
mss = (DAC_COM_LDA | (HI_NYBBLE(dVal)));
break;
case COM_LDB:
mss = (DAC_COM_LDB | (HI_NYBBLE(dVal)));
break;
case COM_LDAB:
mss = (DAC_COM_LDAB | (HI_NYBBLE(dVal)));
break;
default:
break;
}
lss = (NYB_CAT(dVal, LSB_FRAME)); //Form LSB side of header
//Push output to DAC
CLR_BITS(SPI_PORT, SPI_SS);
putSPI(mss);
putSPI(lss);
SET_BITS(SPI_PORT, SPI_SS);
}
/*************************************************************************
Author: Josiah Snarr
Date: April 9, 2015
DACStandby puts the DAC on standby
*************************************************************************/
void DACStandby(void)
{
CLR_BITS(SPI_PORT, SPI_SS);
putSPI(DAC_COM_STAN);
putSPI(LSB_FRAME);
SET_BITS(SPI_PORT, SPI_SS);
}
/*************************************************************************
Author: Josiah Snarr
Date: April 9, 2015
DACShutdown shuts down the DAC
*************************************************************************/
void DACShutdown(void)
{
CLR_BITS(SPI_PORT, SPI_SS);
putSPI(DAC_COM_SHUT);
putSPI(LSB_FRAME);
SET_BITS(SPI_PORT, SPI_SS);
}
/*************************************************************************
Author: Josiah Snarr
Date: April 9, 2015
DACWake wakes the DAC
*************************************************************************/
void DACWake(void)
{
CLR_BITS(SPI_PORT, SPI_SS);
putSPI(DAC_COM_WAKE);
putSPI(LSB_FRAME);
SET_BITS(SPI_PORT, SPI_SS);
}
/**
* For talking to the MCP4822 DAC
*/
void DAC_updateVoltage(uint16_t channel, uint16_t value) {
// Validate channel selection
if(channel <= 1) {
// Cap value to 12 bits only
if(value > 0x0FFF) {
value = 0x0FFF;
}
char txBuf[2];
uint16_t cmd = 0x3000 | (value & 0x0FFF);
if(channel) cmd |= 0x8000;
txBuf[1] = cmd & 0x00FF;
txBuf[0] = __swap_bytes(cmd) & 0x00FF;
CLR_BITS(SPI_PORT(OUT),SSEL | nLDAC); // CS~ falling edge, hold nLDAC low
SPI_send(txBuf, 2);
SET_BITS(SPI_PORT(OUT),SSEL); // CS~ Rising edge. Because nLDAC is low, DAC output changes on rising CS~ edge.
}
}
void
usbs_at91_endpoint_init (usbs_rx_endpoint * pep, cyg_uint8 endpoint_type,
cyg_bool enable)
{
int epn = usbs_at91_pep_to_number(pep);
cyg_addrword_t pCSR = pCSRn(epn);
CYG_ASSERT (AT91_USB_ENDPOINTS > epn, "Invalid end point");
usbs_at91_endpoint_interrupt_enable (epn, false);
/* Reset endpoint */
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 1 << epn);
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_RST_EP, 0);
pep->halted = false;
/* Type | In */
HAL_WRITE_UINT32 (pCSR, (((((cyg_uint32) endpoint_type) & 0x03) << 8) |
((((cyg_uint32) endpoint_type) & 0x80) << 3)));
usbs_at91_endpoint_bytes_in_fifo[epn] = 0;
usbs_at91_endpoint_bytes_received[epn] = THERE_IS_A_NEW_PACKET_IN_THE_UDP;
usbs_at91_endpoint_bank1[epn] = false;
if (enable) {
SET_BITS (pCSR, AT91_UDP_CSR_EPEDS);
}
}
static void
usbs_at91_endpoint_set_halted (usbs_rx_endpoint * pep, cyg_bool new_value)
{
int epn = usbs_at91_pep_to_number(pep);
cyg_addrword_t pCSR = pCSRn(epn);
cyg_drv_dsr_lock ();
if (pep->halted != new_value) {
/* There is something is to do */
pep->halted = new_value;
if (new_value && BITS_ARE_SET (pIMR, 1 << epn)) {
/* Ready to transmit */
if (pep->complete_fn) {
(*pep->complete_fn) (pep->complete_data, -EAGAIN);
}
usbs_at91_endpoint_interrupt_enable (epn, false);
SET_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
} else {
CLEAR_BITS (pCSR, AT91_UDP_CSR_FORCESTALL);
}
}
cyg_drv_dsr_unlock ();
}
// Perform transmit handling on an endpoint
static bool
usbs_at91_endpoint_isr_tx(cyg_uint8 epn)
{
cyg_addrword_t pCSR = pCSRn(epn);
cyg_addrword_t pFDR = pFDRn(epn);
cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[epn];
cyg_uint8 **ppend = &usbs_at91_endpoint_pend[epn];
cyg_uint32 space = 0;
cyg_uint16 endpoint_size = usbs_at91_endpoint_fifo_size[epn];
CLEAR_BITS (pCSR, AT91_UDP_CSR_TXCOMP);
if (BITS_ARE_CLEARED (pCSR, AT91_UDP_CSR_TXPKTRDY)) {
/* Ready to transmit ? */
if (*ppend > *ppbegin) {
/* Something to send */
space = (cyg_uint32) * ppend - (cyg_uint32) * ppbegin;
if (space == endpoint_size) {
*ppend = *ppbegin; /* Send zero-packet */
}
*ppbegin =
write_fifo_uint8 (pFDR, *ppbegin,
(cyg_uint8 *) ((cyg_uint32) * ppbegin +
MIN (space, endpoint_size)));
SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY);
if (*ppend == *ppbegin) { /* Last packet ? */
*ppend = *ppbegin - 1; /* The packet isn't sent yet */
}
} else {
if (*ppend + 1 == *ppbegin) {
*ppend = *ppbegin; /* Flag for DSR */
return true;
} else {
*ppend = *ppbegin - 1; /* Flag for zero-packet */
SET_BITS (pCSR, AT91_UDP_CSR_TXPKTRDY); /* Send no data */
}
}
}
CLEAR_BITS (pCSR,
AT91_UDP_CSR_RX_DATA_BK0 | AT91_UDP_CSR_RX_DATA_BK1 |
AT91_UDP_CSR_RXSETUP | AT91_UDP_CSR_ISOERROR);
return false;
}
/* Initialize timer module */
void timer_init(void) {
timer_overflow_count = 0; // Reset overflow counter
//TOI_ENABLE; // Enable TCNT overflow interrupt
SET_TCNT_PRESCALE(TCNT_PRESCALE_8); // Set timer prescaler
SET_BITS(TSCR1,TSCR1_INIT); // Set timer operation modes and enable timer
}
extern void eo_absCalibratedEncoder_ResetCalibration(EOabsCalibratedEncoder* o)
{
//o->offset = 0; --> dangerous, cause the axis position sharply change (even if I'm in position ctrl mode)
SET_BITS(o->state_mask, SM_NOT_CALIBRATED);
RST_BITS(o->state_mask, SM_NOT_INITIALIZED);
//should I clear the faults too?
RST_BITS(o->state_mask,SM_HARDWARE_FAULT);
}
/*************************************************************************
Author: Josiah Snarr
Date: April 11, 2015
stepperInit initializes the ports which the stepper motor uses, PORTT and
PORTAD
*************************************************************************/
void stepperInit(void)
{
SET_BITS(STEP_DDR, STEP_OUT);
SET_BITS(SMEN_DDR, SMEN_MASK);
SET_BITS(STEP_SWI_DIS, STEP_SWI_IN);
CLR_BITS(STEP_SWI_DDR, STEP_SWI_IN);
MAKE_CHNL_OC(TIOS_IOS4_MASK);
TIE &= (~((unsigned char)TIOS_IOS4_MASK)); //Disable interrupts
SET_BITS(SMEN_PORT, SMEN_MASK);
//Initial direction left, and start at beginning of table
direction = DIR_LEFT;
stepIndex = 0;
stepperHome();
}
static int sunxi_clk_fators_enable(struct clk_hw *hw)
{
struct sunxi_clk_factors *factor = to_clk_factor(hw);
struct sunxi_clk_factors_config *config = factor->config;
unsigned long reg = factor_readl(factor,factor->reg);
unsigned int loop = 300;
unsigned long flags = 0;
if(factor->lock)
spin_lock_irqsave(factor->lock, flags);
if(config->sdmwidth)
{
factor_writel(factor,config->sdmval, (void __iomem *)config->sdmpat);
reg = SET_BITS(config->sdmshift, config->sdmwidth, reg, 1);
}
//enable the register
reg = SET_BITS(config->enshift, 1, reg, 1);
if(config->updshift) //update for pll_ddr register
reg = SET_BITS(config->updshift, 1, reg, 1);
factor_writel(factor,reg, factor->reg);
while(loop--)
{
reg = factor_readl(factor,factor->lock_reg);
if(GET_BITS(factor->lock_bit, 1, reg))
break;
else
udelay(10);
}
if(factor->lock)
spin_unlock_irqrestore(factor->lock, flags);
if(!loop)
#if (defined CONFIG_FPGA_V4_PLATFORM) || (defined CONFIG_FPGA_V7_PLATFORM)
printk("clk %s wait lock timeout\n",hw->clk->name);
#else
WARN(1, "clk %s wait lock timeout\n",hw->clk->name);
#endif
return 0;
}
/* Initialize stepper motor control */
void stepper_init(void) {
// Set initial delay time and step type
stepper_delay = STEPPER_DELAY_INIT;
stepper_step_type = STEPPER_STEP_INIT;
// Enable timer module if not already enabled
if(!(TSCR1 & TSCR1_TEN_MASK)) EnableTimer;
TC_OC(TC_STEPPER); // Channel set to output compare
SET_OC_ACTION(TC_STEPPER,OC_OFF); // Do not change output line after output compare triggered, this is controlled manually
TC(TC_STEPPER) = TCNT + TIMER_DELTA(stepper_delay); // Preset OC channel
TC_INT_ENABLE(TC_STEPPER); // Enable timer channel interrupts
SET_BITS(STEPPER_PORT_DDR,STEPPER_COIL_BITS); // Set stepper coil lines as outputs
SET_BITS(STEPPER_LIMIT_INPUT_EN,STEPPER_LIMIT_INPUT_EN_MASK); // Set limit switch ports as inputs
}
