/*
* enable_galileo_irq
*
* Enables the IRQ on Galileo Chip
*
* Inputs :
* int_cause - The interrupt cause number. In EVB64120 two parameters
* are declared, INT_CAUSE_MAIN and INT_CAUSE_HIGH.
* bit_num - Indicates which bit number in the cause register
*
* Outputs :
* 1 if succesful, 0 if failure
*/
int enable_galileo_irq(int int_cause, int bit_num)
{
if (int_cause == INT_CAUSE_MAIN)
SET_REG_BITS(CPU_INTERRUPT_MASK_REGISTER, (1 << bit_num));
else if (int_cause == INT_CAUSE_HIGH)
SET_REG_BITS(CPU_HIGH_INTERRUPT_MASK_REGISTER,
(1 << bit_num));
else
return 0;
return 1;
}
/**
* Send an ethernet packet. Function will block until
* transmission has completed.
* TODO: Return if the transmission was successful or not
*/
void enc_send_packet(const uint8_t *buf, uint16_t count) {
WRITE_REG(ENC_ETXSTL, TX_START & 0xFF);
WRITE_REG(ENC_ETXSTH, TX_START >> 8);
WRITE_REG(ENC_EWRPTL, TX_START & 0xFF);
WRITE_REG(ENC_EWRPTH, TX_START >> 8);
uint8_t control = 0x00;
enc_wbm(&control, 1);
enc_wbm(buf, count);
uint16_t tx_end = TX_START + count;
WRITE_REG(ENC_ETXNDL, tx_end & 0xFF);
WRITE_REG(ENC_ETXNDH, tx_end >> 8);
/* Eratta 12 */
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_EIR, ENC_EIR_TXIF);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRTS);
/* Busy wait for the transmission to complete
while (true) {
uint8_t r = READ_REG(ENC_ECON1);
if ((r & ENC_ECON1_TXRTS) == 0) break;
}*/
//block until transmission completes to prevent starting new send
while(READ_REG(ENC_ECON1) & ENC_ECON1_TXRTS);
/* Read status bits */
uint8_t status[7];
tx_end++;
WRITE_REG(ENC_ERDPTL, tx_end & 0xFF);
WRITE_REG(ENC_ERDPTH, tx_end >> 8);
enc_rbm(status, 7);
//uint16_t transmit_count = status[0] | (status[1] << 8);
/*if (status[2] & 0x80) {
//Transmit OK
//printf("Transmit OK\n");
}*/
}
/**
* Receive a single packet.
* The contents will be placed in uip_buf, and uIP is called
* as appropriate.
*/
void enc_receive_packet(void) {
/* Receive a single packet */
uint8_t header[6];
uint8_t *status = header + 2;
WRITE_REG(ENC_ERDPTL, enc_next_packet & 0xFF);
WRITE_REG(ENC_ERDPTH, (enc_next_packet >> 8) & 0xFF);
enc_rbm(header, 6);
/* Update next packet pointer */
enc_next_packet = header[0] | (header[1] << 8);
uint16_t data_count = status[0] | (status[1] << 8);
if (status[2] & (1 << 7)) {
uip_len = data_count;
enc_rbm(uip_buf, data_count);
if( BUF->type == htons(UIP_ETHTYPE_IP) ) {
uip_arp_ipin();
uip_input();
if( uip_len > 0 ) {
uip_arp_out();
enc_send_packet(uip_buf, uip_len);
uip_len = 0;
}
} else if( BUF->type == htons(UIP_ETHTYPE_ARP) ) {
uip_arp_arpin();
if( uip_len > 0 ) {
//uip_arp_out();
enc_send_packet(uip_buf, uip_len);
uip_len = 0;
}
}
}
uint16_t erxst = READ_REG(ENC_ERXSTL) | (READ_REG(ENC_ERXSTH) << 8);
/* Mark packet as read */
if (enc_next_packet == erxst) {
WRITE_REG(ENC_ERXRDPTL, READ_REG(ENC_ERXNDL));
WRITE_REG(ENC_ERXRDPTH, READ_REG(ENC_ERXNDH));
} else {
WRITE_REG(ENC_ERXRDPTL, (enc_next_packet-1) & 0xFF);
WRITE_REG(ENC_ERXRDPTH, ((enc_next_packet-1) >> 8) & 0xFF);
}
SET_REG_BITS(ENC_ECON2, ENC_ECON2_PKTDEC);
}
void xge_mac_set_speed(struct xge_pdata *pdata)
{
u32 icm0, icm2, ecm0, mc2;
u32 intf_ctrl, rgmii;
icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
rgmii = xge_rd_csr(pdata, RGMII_REG_0);
mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
icm2 |= CFG_WAITASYNCRD_EN;
switch (pdata->phy_speed) {
case SPEED_10:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
SET_REG_BITS(&icm0, CFG_MACMODE, 0);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
case SPEED_100:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
SET_REG_BITS(&icm0, CFG_MACMODE, 1);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
default:
SET_REG_BITS(&mc2, INTF_MODE, 2);
SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
SET_REG_BITS(&icm0, CFG_MACMODE, 2);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
break;
}
mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
xge_wr_csr(pdata, RGMII_REG_0, rgmii);
xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
}
/**
* Initialize the ENC28J60 with the given MAC-address
*/
void enc_init(const uint8_t *mac) {
enc_next_packet = 0x000;
//MAP_GPIOPinWrite(ENC_RESET_PORT, ENC_RESET, ENC_RESET);
enc_reset();
uint8_t reg;
do {
reg = READ_REG(ENC_ESTAT);
delayMs(200);
printf("ENC_ESTAT: %x\n", reg);
} while ((reg & ENC_ESTAT_CLKRDY) == 0);
enc_switch_bank(0);
printf("Econ: %x\n", READ_REG(ENC_ECON1));
#if 1
printf("Silicon Revision: %d\n", READ_REG(ENC_EREVID));
#endif
//SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
SET_REG_BITS(ENC_ECON2, ENC_ECON2_AUTOINC);
enc_set_rx_area(0x000, RX_END);
uint16_t phyreg = enc_phy_read(ENC_PHSTAT2);
phyreg &= ~ENC_PHSTAT2_DPXSTAT;
enc_phy_write(ENC_PHSTAT2, phyreg);
phyreg = enc_phy_read(ENC_PHCON1);
phyreg &= ~ENC_PHCON_PDPXMD;
enc_phy_write(ENC_PHCON1, phyreg);
/* Setup receive filter to receive
* broadcast, multicast and unicast to the given MAC */
enc_set_mac_addr(mac);
WRITE_REG(
ENC_ERXFCON,
ENC_ERXFCON_UCEN | ENC_ERXFCON_CRCEN |ENC_ERXFCON_MCEN | ENC_ERXFCON_BCEN);
/* Initialize MAC */
WRITE_REG(ENC_MACON1,
ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS | ENC_MACON1_MARXEN);
WRITE_REG(
ENC_MACON3,
(0x1 << ENC_MACON3_PADCFG_SHIFT) | ENC_MACON3_TXRCEN |
/*ENC_MACON3_FULDPX |*/ENC_MACON3_FRMLNEN);
WRITE_REG(ENC_MAMXFLL, 1518 & 0xFF);
WRITE_REG(ENC_MAMXFLH, (1518 >> 8) & 0xFF);
WRITE_REG(ENC_MABBIPG, 0x12);
WRITE_REG(ENC_MAIPGL, 0x12);
WRITE_REG(ENC_MAIPGH, 0x0C);
SET_REG_BITS(ENC_EIE, ENC_EIE_INTIE | ENC_EIE_PKTIE);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
}
