/**************************************************************************
内部函数
**************************************************************************/
s32 bsp_init_poll(u32 u32PoolType)
{
MEM_ALLOC_INFO* pAllocInfo = MEM_GET_ALLOC_INFO(u32PoolType);
/* 分配基地址和大小 */
switch((MEM_POOL_TYPE)u32PoolType)
{
case MEM_NORM_DDR_POOL:
{
/* pAllocInfo->memPoolInfo.u32CurPosAddr =
pAllocInfo->memPoolInfo.u32BaseAddr = (u32)MEM_NORM_DDR_POOL_BASE_ADDR;
pAllocInfo->memPoolInfo.u32Left =
pAllocInfo->memPoolInfo.u32Size = MEM_NORM_DDR_POOL_SIZE;
pAllocInfo->memPoolInfo.u32MgrSize = MEM_MGR_SIZE_FOR_CACHE;
*/
}
break;
case MEM_ICC_DDR_POOL:
{
pAllocInfo->memPoolInfo.u32CurPosAddr =
pAllocInfo->memPoolInfo.u32BaseAddr = (u32)SHD_DDR_V2P(MEM_ICC_DDR_POOL_BASE_ADDR);
pAllocInfo->memPoolInfo.u32Left =
pAllocInfo->memPoolInfo.u32Size = MEM_ICC_DDR_POOL_SIZE;
pAllocInfo->memPoolInfo.u32MgrSize = MEM_MGR_SIZE_FOR_CACHE;
}
break;
case MEM_ICC_AXI_POOL:
{
/* pAllocInfo->memPoolInfo.u32CurPosAddr =
pAllocInfo->memPoolInfo.u32BaseAddr = (u32)DRV_AXI_VIRT_TO_PHY(MEM_ICC_AXI_POOL_BASE_ADDR);
pAllocInfo->memPoolInfo.u32Left =
pAllocInfo->memPoolInfo.u32Size = MEM_ICC_AXI_POOL_SIZE;
pAllocInfo->memPoolInfo.u32MgrSize = MEM_MGR_SIZE_FOR_CACHE;
*/
}
break;
default:
printk("Invalid pool type:%d, line:%d\n", u32PoolType, __LINE__);
return FAIL;
}
if(u32PoolType == MEM_ICC_DDR_POOL)
{
if (!pAllocInfo->memPoolInfo.u32BaseAddr )
{
printk("Invalid pool ptr, line:%d\n", __LINE__);
return FAIL;
}
/* 初始化其他全局变量 */
pAllocInfo->mostUsedItem = 0;
}
return OK;
}
void bsp_memory_free(u32 u32PoolType, void* pMem, u32 u32Size)
{
u32 cnt;
u32 u32MostUsedItem;
MEM_ALLOC_INFO* pAllocInfo = MEM_GET_ALLOC_INFO(u32PoolType);
u32MostUsedItem = pAllocInfo->mostUsedItem;
/* 先查找AllocList中是否有可用的内存节点 */
MEM_FIND_RIGHT_ITEM(cnt, u32Size, u32MostUsedItem);
#ifdef __BSP_MEM_DEBUG__
/* 判断该节点是否有效 */
if (cnt >= MEM_ALLOC_LIST_NUM)
{
printk("bsp_pool_alloc Fail, size:%d, line:%d\n", u32Size, __LINE__);
return;
}
#endif
MEM_LOCK_BY_TYPE(u32PoolType);
/* 将item挂回到链表 */
if (MEM_ICC_AXI_POOL == u32PoolType)
{
MEM_ITEM_NEXT(pMem) = (u32)(pAllocInfo->allocList[cnt]);
pAllocInfo->allocList[cnt] = (void*)(DRV_AXI_VIRT_TO_PHY((u32)pMem));
}
else if (MEM_ICC_DDR_POOL == u32PoolType)
{
MEM_ITEM_NEXT(pMem) = (u32)(pAllocInfo->allocList[cnt]);
pAllocInfo->allocList[cnt] = (void *)SHD_DDR_V2P((u32)pMem);
}
#ifdef __BSP_MEM_DEBUG__
pAllocInfo->allocUsedInfoList[cnt].u32CurNum--;
pAllocInfo->allocUsedInfoList[cnt].u32TotalFreeNum++;
MEM_ITEM_STATUS(pMem) = MEM_FREE;
#endif
/* Flush Cache */
MEM_FLUSH_CACHE_BY_TYPE(MEM_GET_ALLOC_ADDR(pMem), MEM_MGR_SIZE_FOR_CACHE, u32PoolType);
MEM_UNLOCK_BY_TYPE(u32PoolType);
return;
}
/*****************************************************************************
函 数 名 : DRV_DDR_VIRT_TO_PHY
功能描述 : DDR内存虚地址往实地址转换
输入参数 : ulVAddr；虚地址
输出参数 : 无
返回值 ：实地址
*****************************************************************************/
unsigned int DRV_DDR_VIRT_TO_PHY(unsigned int ulVAddr)
{
if((ulVAddr >= DDR_SHARED_MEM_VIRT_ADDR)
&& (ulVAddr < SHM_MEM_TOP_ADDR))
{
return SHD_DDR_V2P(ulVAddr);
}
/* coverity[unsigned_compare] */
if((ulVAddr >= DDR_GU_ADDR_VIRT)/*lint !e685 !e568 */
&& (ulVAddr <= DDR_GU_ADDR_VIRT + DDR_GU_SIZE))
{
return (ulVAddr - DDR_GU_ADDR_VIRT + DDR_GU_ADDR);
}
printk("DRV_DDR_VIRT_TO_PHY: ulVAddr(0x%x) is invalid!\n", ulVAddr);
return 0;
}
/*****************************************************************************
函 数 名 : DRV_DDR_VIRT_TO_PHY
功能描述 : DDR内存虚地址往实地址转换
输入参数 : ulVAddr；虚地址
输出参数 : 无
返回值 ：实地址
*****************************************************************************/
void* DRV_DDR_VIRT_TO_PHY(void* ulVAddr)
{
if(((u32)ulVAddr >= (u32)DDR_SHARED_MEM_VIRT_ADDR)
&& ((u32)ulVAddr < (u32)SHM_MEM_TOP_ADDR))
{
return (void*)SHD_DDR_V2P(ulVAddr);
}
/* coverity[unsigned_compare] */
if(((u32)ulVAddr >= (u32)DDR_GU_ADDR_VIRT)/*lint !e685 !e568 */
&& ((u32)ulVAddr <= (u32)DDR_GU_ADDR_VIRT + DDR_GU_SIZE))
{
return (void*)((u32)ulVAddr - (u32)DDR_GU_ADDR_VIRT + DDR_GU_ADDR);
}
printk("DRV_DDR_VIRT_TO_PHY: ulVAddr(0x%p) is invalid!\n", ulVAddr);
return NULL;
}
void show_shared_ddr_status(void)
{
/*请依照先后顺序增加打印输出项*/
int total_size = SHM_MEM_APPA9_PM_BOOT_SIZE + SHM_MEM_MDMA9_PM_BOOT_SIZE + SHM_MEM_SYNC_SIZE + SHM_MEM_ICC_SIZE +
SHM_MEM_IPF_SIZE + SHM_MEM_WAN_SIZE + SHM_MEM_NV_SIZE + SHM_MEM_M3_MNTN_SIZE +
SHM_MEM_HIFI_SIZE + SHM_MEM_HIFI_MBX_SIZE + SHM_DDM_LOAD_SIZE + SHM_TIMESTAMP_SIZE +
SHM_MEM_IOS_SIZE + SHM_MEM_MODEM_PINTRL_SIZE + SHM_MEM_TEMPERATURE_SIZE +SHM_MEM_RESTORE_AXI_SIZE +
SHM_MEMMGR_FLAG_SIZE + SHM_PMU_OCP_INFO_SIZE + SHM_PMU_VOLTTABLE_SIZE + SHM_MEM_HW_VER_SIZE +
SHM_MEM_PTABLE_SIZE + SHM_MEM_MEMMGR_SIZE + SHM_MEM_NAND_SPEC_SIZE +CORESHARE_MEM_TENCILICA_MULT_BAND_SIZE;
printf("%-30s%10s%10s%10s\n", "name", "phy addr", "virt addr", "size");
printf("%-30s%10x%10x%10x\n", "SHM_MEM_APPA9_PM_BOOT_ADDR", SHD_DDR_V2P(SHM_MEM_APPA9_PM_BOOT_ADDR), SHM_MEM_APPA9_PM_BOOT_ADDR, SHM_MEM_APPA9_PM_BOOT_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MDMA9_PM_BOOT_ADDR", SHD_DDR_V2P(SHM_MEM_MDMA9_PM_BOOT_ADDR), SHM_MEM_MDMA9_PM_BOOT_ADDR, SHM_MEM_MDMA9_PM_BOOT_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_SYNC_ADDR", SHD_DDR_V2P(SHM_MEM_SYNC_ADDR), SHM_MEM_SYNC_ADDR, SHM_MEM_SYNC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_ICC_ADDR", SHD_DDR_V2P(SHM_MEM_ICC_ADDR), SHM_MEM_ICC_ADDR, SHM_MEM_ICC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_IPF_ADDR", SHD_DDR_V2P(SHM_MEM_IPF_ADDR),SHM_MEM_IPF_ADDR, SHM_MEM_IPF_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_WAN_ADDR", SHD_DDR_V2P(SHM_MEM_WAN_ADDR), SHM_MEM_WAN_ADDR, SHM_MEM_WAN_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_NV_ADDR", SHD_DDR_V2P(SHM_MEM_NV_ADDR), SHM_MEM_NV_ADDR, SHM_MEM_NV_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_M3_MNTN_ADDR", SHD_DDR_V2P(SHM_MEM_M3_MNTN_ADDR), SHM_MEM_M3_MNTN_ADDR, SHM_MEM_M3_MNTN_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HIFI_ADDR", SHD_DDR_V2P(SHM_MEM_HIFI_ADDR), SHM_MEM_HIFI_ADDR, SHM_MEM_HIFI_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HIFI_MBX_ADDR", SHD_DDR_V2P(SHM_MEM_HIFI_MBX_ADDR), SHM_MEM_HIFI_MBX_ADDR, SHM_MEM_HIFI_MBX_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_DDM_LOAD_ADDR", SHD_DDR_V2P(SHM_DDM_LOAD_ADDR), SHM_DDM_LOAD_ADDR, SHM_DDM_LOAD_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_TIMESTAMP_ADDR", SHD_DDR_V2P(SHM_TIMESTAMP_ADDR), SHM_TIMESTAMP_ADDR, SHM_TIMESTAMP_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_IOS_ADDR", SHD_DDR_V2P(SHM_MEM_IOS_ADDR), SHM_MEM_IOS_ADDR, SHM_MEM_IOS_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MODEM_PINTRL_ADDR", SHD_DDR_V2P(SHM_MEM_MODEM_PINTRL_ADDR), SHM_MEM_MODEM_PINTRL_ADDR, SHM_MEM_MODEM_PINTRL_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_TEMPERATURE_ADDR", SHD_DDR_V2P(SHM_MEM_TEMPERATURE_ADDR), SHM_MEM_TEMPERATURE_ADDR, SHM_MEM_TEMPERATURE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_RESTORE_AXI_ADDR", SHD_DDR_V2P(SHM_MEM_RESTORE_AXI_ADDR), SHM_MEM_RESTORE_AXI_ADDR, SHM_MEM_RESTORE_AXI_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEMMGR_FLAG_ADDR", SHD_DDR_V2P(SHM_MEMMGR_FLAG_ADDR), SHM_MEMMGR_FLAG_ADDR, SHM_MEMMGR_FLAG_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_PMU_OCP_INFO_ADDR", SHD_DDR_V2P(SHM_PMU_OCP_INFO_ADDR), SHM_PMU_OCP_INFO_ADDR, SHM_PMU_OCP_INFO_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_PMU_VOLTTABLE_ADDR", SHD_DDR_V2P(SHM_PMU_VOLTTABLE_ADDR), SHM_PMU_VOLTTABLE_ADDR, SHM_PMU_VOLTTABLE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_HW_VER_ADDR", SHD_DDR_V2P(SHM_MEM_HW_VER_ADDR), SHM_MEM_HW_VER_ADDR, SHM_MEM_HW_VER_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_DSP_FLAG_ADDR", SHD_DDR_V2P(SHM_MEM_DSP_FLAG_ADDR), SHM_MEM_DSP_FLAG_ADDR, SHM_MEM_DSP_FLAG_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_PTABLE_ADDR", SHD_DDR_V2P(SHM_MEM_PTABLE_ADDR), SHM_MEM_PTABLE_ADDR, SHM_MEM_PTABLE_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_PASTAR_DPM_INFO_ADDR", SHD_DDR_V2P(SHM_MEM_PASTAR_DPM_INFO_ADDR), SHM_MEM_PASTAR_DPM_INFO_ADDR, SHM_MEM_PASTAR_DPM_INFO_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_LOADM_ADDR", SHD_DDR_V2P(SHM_MEM_LOADM_ADDR), SHM_MEM_LOADM_ADDR, SHM_MEM_LOADM_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_NAND_SPEC_ADDR", SHD_DDR_V2P(SHM_MEM_NAND_SPEC_ADDR), SHM_MEM_NAND_SPEC_ADDR, SHM_MEM_NAND_SPEC_SIZE);
printf("%-30s%10x%10x%10x\n", "SHM_MEM_MEMMGR_ADDR", SHD_DDR_V2P(SHM_MEM_MEMMGR_ADDR), SHM_MEM_MEMMGR_ADDR, SHM_MEM_MEMMGR_SIZE);
printf("%-30s%10x%10x%10x\n", "CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR", CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR, SHD_DDR_P2V(CORESHARE_MEM_TENCILICA_MULT_BAND_ADDR), CORESHARE_MEM_TENCILICA_MULT_BAND_SIZE);/*lint !e778 */
printf("total size: 0x%x\n", total_size);
}
s32 hifi2_stress_test_start(void)
{
u32 readlen = 0;
unsigned int handle;
mm_segment_t oldfs;
u32 buffer[0x10];
long ret = 0;
int error = 0;
error |= bsp_hifi_pll_enable();
error |= bsp_hifi_power_on();
error |= bsp_hifi_clock_enable();
error |= bsp_hifi_unreset();
hifi2_tcm_addr = (u32)ioremap_nocache(HIFI_TCM_ADDR, HIFI_TCM_SIZE);
if (NULL == (void*)hifi2_tcm_addr)
{
printk(KERN_ERR"fail to io remap\n");
return -ENOMEM;
}
oldfs = get_fs();
set_fs(KERNEL_DS);
handle = (unsigned int)sys_open("/data/hifi2", O_RDONLY, 0);
if (IS_ERR((const void*)handle))
{
printk(KERN_ERR"fail to open file '/data/hifi2'\n");
return -1;
}
#ifdef BSP_DSP_BBE16
do
{
ret = sys_read(handle, (char*)buffer, sizeof(buffer));
memcpy((void*)(hifi2_tcm_addr+0x4080+readlen), (void*)buffer, sizeof(buffer));
readlen += ret;
}while(ret == sizeof(buffer));
#else
do
{
ret = sys_read(handle, (char*)buffer, sizeof(buffer));
memcpy((void*)(hifi2_tcm_addr+readlen), (void*)buffer, sizeof(buffer));
readlen += ret;
}while(ret == sizeof(buffer));
#endif
sys_close(handle);
set_fs(oldfs);
#if 0
#ifdef BSP_DSP_BBE16
/* HiFi2 DMEM1Æ«ÒÆ0x4000(16KB) */
writel(DDR_TLPHY_IMAGE_ADDR, hifi2_tcm_addr+0x4000);
writel(1024/4, hifi2_tcm_addr+0x4004);
writel(AXI_MEM_64_SRC_FOR_HIFI_PHY, hifi2_tcm_addr+0x4008);
writel(AXI_MEM_64_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x400C);
writel(AXI_MEM_FOR_HIFI_SRC_ADDR_PHY, hifi2_tcm_addr+0x4010);
writel(AXI_MEM_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x4014);
writel(0, hifi2_tcm_addr+0x401C);
#else
/* HiFi2 DMEM1Æ«ÒÆ0x8000(32KB) */
writel(DDR_TLPHY_IMAGE_ADDR, hifi2_tcm_addr+0x8000);
writel(1024/4, hifi2_tcm_addr+0x8004);
writel(AXI_MEM_64_SRC_FOR_HIFI_PHY, hifi2_tcm_addr+0x8008);
writel(AXI_MEM_64_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x800C);
writel(AXI_MEM_FOR_HIFI_SRC_ADDR_PHY, hifi2_tcm_addr+0x8010);
writel(AXI_MEM_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x8014);
writel(0, hifi2_tcm_addr+0x801C);
set_hi_sc_ctrl12_hifi_runstall(0);
#endif
#endif
/* HiFi2 DMEM1Æ«ÒÆ0x8000(32KB) */
writel(SHD_DDR_V2P(HIFI_DDR_BASEADDR), hifi2_tcm_addr+0x8000);
writel(HIFI_DDR_SIZE/4, hifi2_tcm_addr+0x8004);
writel(AXI_MEM_64_SRC_FOR_HIFI_PHY, hifi2_tcm_addr+0x8008);
writel(AXI_MEM_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x800C);
writel(AXI_MEM_FOR_HIFI_SRC_ADDR_PHY, hifi2_tcm_addr+0x8010);
writel(AXI_MEM_FOR_MEMCPY_SIZE*2/4, hifi2_tcm_addr+0x8014);
writel(0, hifi2_tcm_addr+0x801C);
error |= bsp_hifi_run();
printk(KERN_INFO"OK, image length: %d\n", readlen);
return error;
}