/* ====================================================================
*
* TI_RES_RES_Unreserve_Resources
*
* See interface description
*
* ====================================================================
*/
void TI_RES_RES_Unreserve_Resources(
TI_RES_RES *res,
TOP opcode,
INT cycle
)
{
INT cycle_mod_ii;
INT length1;
INT length2;
INT i;
SI_RR rr;
SI_RRW *rrtab = TI_RES_RES_rrtab(res);
Check_Reserve_Loop_Control(res,opcode,cycle,
&rr,&length1,&length2,&cycle_mod_ii);
for ( i = 0; i < length1; ++i ) {
rrtab[cycle_mod_ii+i]
= SI_RRW_Unreserve(rrtab[cycle_mod_ii+i],SI_RR_Cycle_RRW(rr,i));
}
for ( i = 0; i < length2; ++i ) {
rrtab[i] = SI_RRW_Unreserve(rrtab[i],SI_RR_Cycle_RRW(rr,i+length1));
}
}
BOOL TI_RES_RES_Alternative_Resources_Available(
TI_RES_RES *res,
TOP opcode,
INT cycle
)
{
INT cycle_mod_ii;
INT length1;
INT length2;
INT i;
SI_RR rr;
SI_RRW *rrtab = TI_RES_RES_rrtab(res);
Check_Reserve_Loop_Control_For_Alternative_Res(res,opcode,cycle,
&rr,&length1,&length2,&cycle_mod_ii);
for ( i = 0; i < length1; ++i ) {
SI_RRW reserved = SI_RRW_Reserve(rrtab[cycle_mod_ii+i],
SI_RR_Cycle_RRW(rr,i));
if ( SI_RRW_Has_Overuse(reserved) ) return FALSE;
}
for ( i = 0; i < length2; ++i ) {
SI_RRW reserved = SI_RRW_Reserve(rrtab[i],SI_RR_Cycle_RRW(rr,i+length1));
if ( SI_RRW_Has_Overuse(reserved) ) return FALSE;
}
return TRUE;
}
/* ====================================================================
*
* TI_RES_RES_Resources_Equivalent
*
* See interface description
*
* ====================================================================
*/
BOOL TI_RES_RES_Resources_Equivalent(
TI_RES_RES *res,
TOP opcode1,
TOP opcode2
)
{
INT i;
const INT32 length = TI_RES_RES_length(res);
SI_RR rr1 = TSI_II_Resource_Requirement(opcode1,length);
SI_RR rr2 = TSI_II_Resource_Requirement(opcode2,length);
if ( rr1 == rr2 ) return TRUE;
if ( SI_RR_Length(rr1) != SI_RR_Length(rr2) ) return FALSE;
for (i = 0; i < SI_RR_Length(rr1); ++i) {
if ( SI_RR_Cycle_RRW(rr1,i) != SI_RR_Cycle_RRW(rr2,i) )
return FALSE;
}
return TRUE;
}
/* ====================================================================
*
* TI_RES_Can_Dual_Issue
*
* See interface description
*
* ====================================================================
*/
BOOL TI_RES_Can_Dual_Issue(
TOP opcode1,
TOP opcode2
)
{
INT min_length, i;
SI_RR rr1, rr2;
/* Quick check to see if we could ever dual issue something.
*/
if (!PROC_has_same_cycle_branch_shadow()) return FALSE;
/* Resource requirements for each.
*/
rr1 = TSI_Resource_Requirement(opcode1);
rr2 = TSI_Resource_Requirement(opcode2);
/* We only have to check up to the end of the shorter of the two resource
* requests.
*/
if ( SI_RR_Length(rr1) < SI_RR_Length(rr2) )
min_length = SI_RR_Length(rr1);
else
min_length = SI_RR_Length(rr2);
/* Check each cycle.
*/
for ( i = 0; i < min_length; ++i ) {
SI_RRW rrw = SI_RRW_Initial();
rrw = SI_RRW_Reserve(rrw,SI_RR_Cycle_RRW(rr1,i));
rrw = SI_RRW_Reserve(rrw,SI_RR_Cycle_RRW(rr2,i));
if ( SI_RRW_Has_Overuse(rrw) ) return FALSE;
}
return TRUE;
}
