s32 sunximmc_init_controller(struct sunxi_mmc_host* smc_host) { SMC_INFO("MMC Driver init host %d\n", smc_host->pdev->id); sdxc_init(smc_host); return 0; }
/* static s32 sunximmc_set_src_clk(struct sunxi_mmc_host* smc_host) * 设置SD卡控制器源时钟频率, 目标为100MHz,clock源有smc_host的clk_source决定 * clk_source: 0-video PLL, 2-dram PLL, 3-core pll */ static int sunximmc_set_src_clk(struct sunxi_mmc_host* smc_host) { struct clk *source_clock = NULL; char* name[] = {"hosc", "sata_pll_2", "sdram_pll_p", "hosc"}; int ret; switch (smc_host->clk_source) { case 0: case 3: source_clock = clk_get(&smc_host->pdev->dev, "hosc"); break; case 1: source_clock = clk_get(&smc_host->pdev->dev, "sata_pll_2"); break; case 2: source_clock = clk_get(&smc_host->pdev->dev, "sdram_pll_p"); break; } if (IS_ERR(source_clock)) { ret = PTR_ERR(source_clock); SMC_ERR("Error to get source clock %s\n", name[smc_host->clk_source]); return ret; } clk_set_parent(smc_host->mclk, source_clock); clk_set_rate(smc_host->mclk, smc_host->mod_clk); clk_enable(smc_host->mclk); #ifdef CONFIG_SUN5I_FPGA smc_host->mod_clk = 24000000; #else smc_host->mod_clk = clk_get_rate(smc_host->mclk); #endif clk_enable(smc_host->hclk); SMC_INFO("smc %d, source = %s, src_clk = %u, mclk %u, \n", smc_host->pdev->id, name[smc_host->clk_source], (unsigned)clk_get_rate(source_clock), smc_host->mod_clk); clk_put(source_clock); return 0; }