__interrupt void RXISR() {
// UART
if(IFG2 & UCB0RXIFG) {
UARTTransmit(UCB0RXBUF);
}
// SPI
if (IFG2 & UCA0RXIFG) {
SPITransmit(UCA0RXBUF);
}
}
static BOOL MessageDone() {
// TODO: check pin capabilities
switch (rx_msg.type) {
case HARD_RESET:
CHECK(rx_msg.args.hard_reset.magic == IOIO_MAGIC);
HardReset();
break;
case SOFT_RESET:
SoftReset();
Echo();
break;
case SET_PIN_DIGITAL_OUT:
CHECK(rx_msg.args.set_pin_digital_out.pin < NUM_PINS);
SetPinDigitalOut(rx_msg.args.set_pin_digital_out.pin,
rx_msg.args.set_pin_digital_out.value,
rx_msg.args.set_pin_digital_out.open_drain);
break;
case SET_DIGITAL_OUT_LEVEL:
CHECK(rx_msg.args.set_digital_out_level.pin < NUM_PINS);
SetDigitalOutLevel(rx_msg.args.set_digital_out_level.pin,
rx_msg.args.set_digital_out_level.value);
break;
case SET_PIN_DIGITAL_IN:
CHECK(rx_msg.args.set_pin_digital_in.pin < NUM_PINS);
CHECK(rx_msg.args.set_pin_digital_in.pull < 3);
SetPinDigitalIn(rx_msg.args.set_pin_digital_in.pin, rx_msg.args.set_pin_digital_in.pull);
break;
case SET_CHANGE_NOTIFY:
CHECK(rx_msg.args.set_change_notify.pin < NUM_PINS);
if (rx_msg.args.set_change_notify.cn) {
Echo();
}
SetChangeNotify(rx_msg.args.set_change_notify.pin, rx_msg.args.set_change_notify.cn);
if (!rx_msg.args.set_change_notify.cn) {
Echo();
}
break;
case SET_PIN_PWM:
CHECK(rx_msg.args.set_pin_pwm.pin < NUM_PINS);
CHECK(rx_msg.args.set_pin_pwm.pwm_num < NUM_PWM_MODULES);
SetPinPwm(rx_msg.args.set_pin_pwm.pin, rx_msg.args.set_pin_pwm.pwm_num,
rx_msg.args.set_pin_pwm.enable);
break;
case SET_PWM_DUTY_CYCLE:
CHECK(rx_msg.args.set_pwm_duty_cycle.pwm_num < NUM_PWM_MODULES);
SetPwmDutyCycle(rx_msg.args.set_pwm_duty_cycle.pwm_num,
rx_msg.args.set_pwm_duty_cycle.dc,
rx_msg.args.set_pwm_duty_cycle.fraction);
break;
case SET_PWM_PERIOD:
CHECK(rx_msg.args.set_pwm_period.pwm_num < NUM_PWM_MODULES);
SetPwmPeriod(rx_msg.args.set_pwm_period.pwm_num,
rx_msg.args.set_pwm_period.period,
rx_msg.args.set_pwm_period.scale_l
| (rx_msg.args.set_pwm_period.scale_h) << 1);
break;
case SET_PIN_ANALOG_IN:
CHECK(rx_msg.args.set_pin_analog_in.pin < NUM_PINS);
SetPinAnalogIn(rx_msg.args.set_pin_analog_in.pin);
break;
case UART_DATA:
CHECK(rx_msg.args.uart_data.uart_num < NUM_UART_MODULES);
UARTTransmit(rx_msg.args.uart_data.uart_num,
rx_msg.args.uart_data.data,
rx_msg.args.uart_data.size + 1);
break;
case UART_CONFIG:
CHECK(rx_msg.args.uart_config.uart_num < NUM_UART_MODULES);
CHECK(rx_msg.args.uart_config.parity < 3);
UARTConfig(rx_msg.args.uart_config.uart_num,
rx_msg.args.uart_config.rate,
rx_msg.args.uart_config.speed4x,
rx_msg.args.uart_config.two_stop_bits,
rx_msg.args.uart_config.parity);
break;
case SET_PIN_UART:
CHECK(rx_msg.args.set_pin_uart.pin < NUM_PINS);
CHECK(rx_msg.args.set_pin_uart.uart_num < NUM_UART_MODULES);
SetPinUart(rx_msg.args.set_pin_uart.pin,
rx_msg.args.set_pin_uart.uart_num,
rx_msg.args.set_pin_uart.dir,
rx_msg.args.set_pin_uart.enable);
break;
case SPI_MASTER_REQUEST:
CHECK(rx_msg.args.spi_master_request.spi_num < NUM_SPI_MODULES);
CHECK(rx_msg.args.spi_master_request.ss_pin < NUM_PINS);
{
const BYTE total_size = rx_msg.args.spi_master_request.total_size + 1;
const BYTE data_size = rx_msg.args.spi_master_request.data_size_neq_total
? rx_msg.args.spi_master_request.data_size
: total_size;
const BYTE res_size = rx_msg.args.spi_master_request.res_size_neq_total
? rx_msg.args.spi_master_request.vararg[
rx_msg.args.spi_master_request.data_size_neq_total]
: total_size;
const BYTE* const data = &rx_msg.args.spi_master_request.vararg[
rx_msg.args.spi_master_request.data_size_neq_total
+ rx_msg.args.spi_master_request.res_size_neq_total];
SPITransmit(rx_msg.args.spi_master_request.spi_num,
rx_msg.args.spi_master_request.ss_pin,
data,
data_size,
total_size,
total_size - res_size);
}
break;
case SPI_CONFIGURE_MASTER:
CHECK(rx_msg.args.spi_configure_master.spi_num < NUM_SPI_MODULES);
SPIConfigMaster(rx_msg.args.spi_configure_master.spi_num,
rx_msg.args.spi_configure_master.scale,
rx_msg.args.spi_configure_master.div,
rx_msg.args.spi_configure_master.smp_end,
rx_msg.args.spi_configure_master.clk_edge,
rx_msg.args.spi_configure_master.clk_pol);
break;
case SET_PIN_SPI:
CHECK(rx_msg.args.set_pin_spi.mode < 3);
CHECK((!rx_msg.args.set_pin_spi.enable
&& rx_msg.args.set_pin_spi.mode == 1)
|| rx_msg.args.set_pin_spi.pin < NUM_PINS);
CHECK((!rx_msg.args.set_pin_spi.enable
&& rx_msg.args.set_pin_spi.mode != 1)
|| rx_msg.args.set_pin_spi.spi_num < NUM_SPI_MODULES);
SetPinSpi(rx_msg.args.set_pin_spi.pin,
rx_msg.args.set_pin_spi.spi_num,
rx_msg.args.set_pin_spi.mode,
rx_msg.args.set_pin_spi.enable);
break;
case I2C_CONFIGURE_MASTER:
CHECK(rx_msg.args.i2c_configure_master.i2c_num < NUM_I2C_MODULES);
I2CConfigMaster(rx_msg.args.i2c_configure_master.i2c_num,
rx_msg.args.i2c_configure_master.rate,
rx_msg.args.i2c_configure_master.smbus_levels);
break;
case I2C_WRITE_READ:
CHECK(rx_msg.args.i2c_write_read.i2c_num < NUM_I2C_MODULES);
{
unsigned int addr;
if (rx_msg.args.i2c_write_read.ten_bit_addr) {
addr = rx_msg.args.i2c_write_read.addr_lsb;
addr = addr << 8
| ((rx_msg.args.i2c_write_read.addr_msb << 1)
| 0b11110000);
} else {
CHECK(rx_msg.args.i2c_write_read.addr_msb == 0
&& rx_msg.args.i2c_write_read.addr_lsb >> 7 == 0
&& rx_msg.args.i2c_write_read.addr_lsb >> 2 != 0b0011110);
addr = rx_msg.args.i2c_write_read.addr_lsb << 1;
}
I2CWriteRead(rx_msg.args.i2c_write_read.i2c_num,
addr,
rx_msg.args.i2c_write_read.data,
rx_msg.args.i2c_write_read.write_size,
rx_msg.args.i2c_write_read.read_size);
}
break;
case SET_ANALOG_IN_SAMPLING:
CHECK(rx_msg.args.set_analog_pin_sampling.pin < NUM_PINS);
ADCSetScan(rx_msg.args.set_analog_pin_sampling.pin,
rx_msg.args.set_analog_pin_sampling.enable);
break;
case CHECK_INTERFACE:
CheckInterface(rx_msg.args.check_interface.interface_id);
break;
case ICSP_SIX:
ICSPSix(rx_msg.args.icsp_six.inst);
break;
case ICSP_REGOUT:
ICSPRegout();
break;
case ICSP_PROG_ENTER:
ICSPEnter();
break;
case ICSP_PROG_EXIT:
ICSPExit();
break;
case ICSP_CONFIG:
if (rx_msg.args.icsp_config.enable) {
Echo();
}
ICSPConfigure(rx_msg.args.icsp_config.enable);
if (!rx_msg.args.icsp_config.enable) {
Echo();
}
break;
case INCAP_CONFIG:
CHECK(rx_msg.args.incap_config.incap_num < NUM_INCAP_MODULES);
CHECK(!rx_msg.args.incap_config.double_prec
|| 0 == (rx_msg.args.incap_config.incap_num & 0x01));
CHECK(rx_msg.args.incap_config.mode < 6);
CHECK(rx_msg.args.incap_config.clock < 4);
InCapConfig(rx_msg.args.incap_config.incap_num,
rx_msg.args.incap_config.double_prec,
rx_msg.args.incap_config.mode,
rx_msg.args.incap_config.clock);
break;
case SET_PIN_INCAP:
CHECK(rx_msg.args.set_pin_incap.incap_num < NUM_INCAP_MODULES);
CHECK(!rx_msg.args.set_pin_incap.enable
|| rx_msg.args.set_pin_incap.pin < NUM_PINS);
SetPinInCap(rx_msg.args.set_pin_incap.pin,
rx_msg.args.set_pin_incap.incap_num,
rx_msg.args.set_pin_incap.enable);
break;
case SOFT_CLOSE:
log_printf("Soft close requested");
Echo();
state = STATE_CLOSING;
break;
case SET_PIN_PULSECOUNTER:
CHECK(rx_msg.args.set_pin_pulsecounter.pin < NUM_PINS);
CHECK(rx_msg.args.set_pin_pulsecounter.mode < 4);
CHECK(rx_msg.args.set_pin_pulsecounter.rateord < 9);
CHECK(rx_msg.args.set_pin_pulsecounter.stepsord < 4);
SetPinPulseCounter(rx_msg.args.set_pin_pulsecounter.pin,
rx_msg.args.set_pin_pulsecounter.enable,
rx_msg.args.set_pin_pulsecounter.mode,
rx_msg.args.set_pin_pulsecounter.rateord,
rx_msg.args.set_pin_pulsecounter.stepsord);
break;
// BOOKMARK(add_feature): Add incoming message handling to switch clause.
// Call Echo() if the message is to be echoed back.
default:
return FALSE;
}
return TRUE;
}
