uint16_t SpiFlash_ReadMidDid(void)
{
uint8_t u8RxData[6], u8IDCnt = 0;
// /CS: active
SPI_SET_SS0_LOW(SPI_FLASH_PORT);
// send Command: 0x90, Read Manufacturer/Device ID
SPI_WRITE_TX(SPI_FLASH_PORT, 0x90);
// send 24-bit '0', dummy
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// receive 16-bit
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
SPI_WRITE_TX(SPI_FLASH_PORT, 0x00);
// wait tx finish
while(SPI_IS_BUSY(SPI_FLASH_PORT));
// /CS: de-active
SPI_SET_SS0_HIGH(SPI_FLASH_PORT);
while(!SPI_GET_RX_FIFO_EMPTY_FLAG(SPI_FLASH_PORT))
u8RxData[u8IDCnt ++] = SPI_READ_RX(SPI_FLASH_PORT);
return ( (u8RxData[4]<<8) | u8RxData[5] );
}
void SPI0_IRQHandler(void)
{
/* Check RX EMPTY flag */
while(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
{
/* Read RX FIFO */
g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX(SPI0);
}
/* Check TX FULL flag and TX data count */
while((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (g_u32TxDataCount < TEST_COUNT))
{
/* Write to TX FIFO */
SPI_WRITE_TX(SPI0, g_au32SourceData[g_u32TxDataCount++]);
}
if(g_u32TxDataCount >= TEST_COUNT)
SPI_DisableInt(SPI0, SPI_FIFO_TX_INT_MASK); /* Disable TX FIFO threshold interrupt */
/* Check the RX FIFO time-out interrupt flag */
if(SPI_GetIntFlag(SPI0, SPI_FIFO_TIMEOUT_INT_MASK))
{
/* If RX FIFO is not empty, read RX FIFO. */
while((SPI0->STATUS & SPI_STATUS_RX_EMPTY_Msk) == 0)
g_au32DestinationData[g_u32RxDataCount++] = SPI_READ_RX(SPI0);
}
}
/* ------------- */
int main(void)
{
volatile uint32_t u32TxDataCount, u32RxDataCount;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O. */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/* Init SPI */
SPI_Init();
printf("\n\n");
printf("+-----------------------------------------------------+\n");
printf("| SPI Slave Mode Sample Code |\n");
printf("+-----------------------------------------------------+\n");
printf("\n");
printf("Configure SPI0 as a slave.\n");
printf("Bit length of a transaction: 32\n");
printf("The I/O connection for SPI0:\n");
printf(" SPI0_SS (PB.4)\n SPI0_CLK (PB.2)\n");
printf(" SPI0_MISO0 (PB.3)\n SPI0_MOSI0 (PB.5)\n\n");
printf("SPI controller will transfer %d data to a off-chip master device.\n", TEST_COUNT);
printf("In the meanwhile the SPI controller will receive %d data from the off-chip master device.\n", TEST_COUNT);
printf("After the transfer is done, the %d received data will be printed out.\n", TEST_COUNT);
for(u32TxDataCount = 0; u32TxDataCount < TEST_COUNT; u32TxDataCount++)
{
/* Write the initial value to source buffer */
g_au32SourceData[u32TxDataCount] = 0x00AA0000 + u32TxDataCount;
/* Clear destination buffer */
g_au32DestinationData[u32TxDataCount] = 0;
}
u32TxDataCount = 0;
u32RxDataCount = 0;
printf("Press any key if the master device configuration is ready.");
getchar();
printf("\n");
/* Access TX and RX FIFO */
while(u32RxDataCount < TEST_COUNT)
{
/* Check TX FULL flag and TX data count */
if((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (u32TxDataCount < TEST_COUNT))
SPI_WRITE_TX(SPI0, g_au32SourceData[u32TxDataCount++]); /* Write to TX FIFO */
/* Check RX EMPTY flag */
if(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
g_au32DestinationData[u32RxDataCount++] = SPI_READ_RX(SPI0); /* Read RX FIFO */
}
/* Print the received data */
printf("Received data:\n");
for(u32RxDataCount = 0; u32RxDataCount < TEST_COUNT; u32RxDataCount++)
{
printf("%d:\t0x%X\n", u32RxDataCount, g_au32DestinationData[u32RxDataCount]);
}
printf("The data transfer was done.\n");
printf("\n\nExit SPI driver sample code.\n");
/* Disable SPI0 peripheral clock */
CLK->APBCLK0 &= (~CLK_APBCLK0_SPI0CKEN_Msk);
while(1);
}
