static void load_ssp_default_config(struct pl022 *pl022) { writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); }
static void restore_state(struct pl022 *pl022) { struct chip_data *chip = pl022->cur_chip; writew(chip->cr0, SSP_CR0(pl022->virtbase)); writew(chip->cr1, SSP_CR1(pl022->virtbase)); writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); writew(chip->cpsr, SSP_CPSR(pl022->virtbase)); writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); }
static void load_ssp_default_config(struct pl022 *pl022) { if (pl022->vendor->pl023) { writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); } else if (pl022->vendor->extended_cr) { writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); } else { writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); } writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase)); writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase)); writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase)); writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase)); }
/* * SSP Init function */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, ssp_frame_format_t frame_format, ssp_cpol_cpha_t cpol_cpha_format, uint8_t serial_clock_rate, uint8_t clk_prescale, ssp_mode_t mode, ssp_master_slave_t master_slave, ssp_slave_option_t slave_option) { uint32_t ssp_port; uint32_t clock; if (ssp_num == SSP0_NUM) { ssp_port = SSP0; CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_SSP0_CLK_AUTOBLOCK; CCU1_CLK_M4_SSP0_CFG |= 1; /* Enable SSP0 Clock */ /* use PLL1 as clock source for SSP0 */ } else { ssp_port = SSP1; /* use PLL1 as clock source for SSP1 */ CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_SSP1_CLK_AUTOBLOCK; CCU1_CLK_M4_SSP1_CFG |= 1; /* Enable SSP1 Clock */ } /* Disable SSP before to configure it */ SSP_CR1(ssp_port) = 0x0; /* Configure SSP */ clock = serial_clock_rate; SSP_CPSR(ssp_port) = clk_prescale; SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8)); /* Enable SSP */ SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option); }