static void sun4i_spi_set_cs(struct spi_device *spi, bool enable)
{
struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
u32 reg;
reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
reg &= ~SUN4I_CTL_CS_MASK;
reg |= SUN4I_CTL_CS(spi->chip_select);
if (enable)
reg |= SUN4I_CTL_CS_LEVEL;
else
reg &= ~SUN4I_CTL_CS_LEVEL;
/*
* Even though this looks irrelevant since we are supposed to
* be controlling the chip select manually, this bit also
* controls the levels of the chip select for inactive
* devices.
*
* If we don't set it, the chip select level will go low by
* default when the device is idle, which is not really
* expected in the common case where the chip select is active
* low.
*/
if (spi->mode & SPI_CS_HIGH)
reg &= ~SUN4I_CTL_CS_ACTIVE_LOW;
else
reg |= SUN4I_CTL_CS_ACTIVE_LOW;
sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
}
static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable)
{
struct sun4i_spi_priv *priv = dev_get_priv(bus);
u32 reg;
reg = readl(&priv->regs->ctl);
reg &= ~SUN4I_CTL_CS_MASK;
reg |= SUN4I_CTL_CS(cs);
if (enable)
reg &= ~SUN4I_CTL_CS_LEVEL;
else
reg |= SUN4I_CTL_CS_LEVEL;
writel(reg, &priv->regs->ctl);
}
