static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) { SH7750State *s = opaque; SuperHCPUClass *scc; switch (addr) { case SH7750_BCR1_A7: return s->bcr1; case SH7750_BCR4_A7: if(!has_bcr3_and_bcr4(s)) error_access("long read", addr); return s->bcr4; case SH7750_WCR1_A7: case SH7750_WCR2_A7: case SH7750_WCR3_A7: case SH7750_MCR_A7: ignore_access("long read", addr); return 0; case SH7750_MMUCR_A7: return s->cpu->env.mmucr; case SH7750_PTEH_A7: return s->cpu->env.pteh; case SH7750_PTEL_A7: return s->cpu->env.ptel; case SH7750_TTB_A7: return s->cpu->env.ttb; case SH7750_TEA_A7: return s->cpu->env.tea; case SH7750_TRA_A7: return s->cpu->env.tra; case SH7750_EXPEVT_A7: return s->cpu->env.expevt; case SH7750_INTEVT_A7: return s->cpu->env.intevt; case SH7750_CCR_A7: return s->ccr; case 0x1f000030: /* Processor version */ scc = SUPERH_CPU_GET_CLASS(s->cpu); return scc->pvr; case 0x1f000040: /* Cache version */ scc = SUPERH_CPU_GET_CLASS(s->cpu); return scc->cvr; case 0x1f000044: /* Processor revision */ scc = SUPERH_CPU_GET_CLASS(s->cpu); return scc->prr; default: error_access("long read", addr); abort(); } }
/* CPUClass::reset() */ static void superh_cpu_reset(CPUState *s) { SuperHCPU *cpu = SUPERH_CPU(s); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); CPUSH4State *env = &cpu->env; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); log_cpu_state(env, 0); } scc->parent_reset(s); memset(env, 0, offsetof(CPUSH4State, breakpoints)); tlb_flush(env, 1); env->pc = 0xA0000000; #if defined(CONFIG_USER_ONLY) env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ #else env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ set_float_rounding_mode(float_round_to_zero, &env->fp_status); set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); }
static void superh_cpu_realizefn(DeviceState *dev, Error **errp) { SuperHCPU *cpu = SUPERH_CPU(dev); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); cpu_reset(CPU(cpu)); qemu_init_vcpu(&cpu->env); scc->parent_realize(dev, errp); }