void
cpu_reset(void)
{
uint32_t ver = SVR_VER(mfspr(SPR_SVR));
if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
ver == SVR_MPC8548E || ver == SVR_MPC8548)
/* Systems with dedicated reset register */
ccsr_write4(OCP85XX_RSTCR, 2);
else {
/* Clear DBCR0, disables debug interrupts and events. */
mtspr(SPR_DBCR0, 0);
__asm __volatile("isync");
/* Enable Debug Interrupts in MSR. */
mtmsr(mfmsr() | PSL_DE);
/* Enable debug interrupts and issue reset. */
mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
DBCR0_RST_SYSTEM);
}
printf("Reset failed...\n");
while (1);
}
int
law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
{
u_long start;
uint32_t ver;
int trgt, rv;
ver = SVR_VER(mfspr(SPR_SVR));
start = rman_get_start(res) & 0xf000;
rv = 0;
trgt = -1;
switch (start) {
case 0x8000:
trgt = 0;
break;
case 0x9000:
trgt = 1;
break;
case 0xa000:
if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
trgt = 2;
else
rv = EINVAL;
break;
default:
rv = ENXIO;
}
*trgt_mem = *trgt_io = trgt;
return (rv);
}
int
law_getmax(void)
{
uint32_t ver;
ver = SVR_VER(mfspr(SPR_SVR));
if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
return (12);
else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
return (10);
else
return (8);
}
int
law_getmax(void)
{
uint32_t ver;
ver = SVR_VER(mfspr(SPR_SVR));
if (ver == SVR_MPC8555E || ver == SVR_MPC8555)
return (8);
if (ver == SVR_MPC8548E || ver == SVR_MPC8548 ||
ver == SVR_MPC8533E || ver == SVR_MPC8533)
return (10);
return (12);
}
static int
bare_probe(platform_t plat)
{
uint32_t ver, sr;
int i, law_max, tgt;
ver = SVR_VER(mfspr(SPR_SVR));
switch (ver & ~0x0008) { /* Mask Security Enabled bit */
case SVR_P4080:
maxcpu = 8;
break;
case SVR_P4040:
maxcpu = 4;
break;
case SVR_MPC8572:
case SVR_P1020:
case SVR_P2020:
maxcpu = 2;
break;
default:
maxcpu = 1;
break;
}
/*
* Clear local access windows. Skip DRAM entries, so we don't shoot
* ourselves in the foot.
*/
law_max = law_getmax();
for (i = 0; i < law_max; i++) {
sr = ccsr_read4(OCP85XX_LAWSR(i));
if ((sr & 0x80000000) == 0)
continue;
tgt = (sr & 0x01f00000) >> 20;
if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
tgt == OCP85XX_TGTIF_RAM_INTL)
continue;
ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff);
}
return (BUS_PROBE_GENERIC);
}
int
checkcpu(void)
{
sys_info_t sysinfo;
uint pvr, svr;
uint ver;
uint major, minor;
uint lcrr; /* local bus clock ratio register */
uint clkdiv; /* clock divider portion of lcrr */
puts("Freescale PowerPC\n");
pvr = get_pvr();
ver = PVR_VER(pvr);
major = PVR_MAJ(pvr);
minor = PVR_MIN(pvr);
puts("CPU:\n");
puts(" Core: ");
switch (ver) {
case PVR_VER(PVR_86xx):
puts("E600");
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
svr = get_svr();
ver = SVR_VER(svr);
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
puts(" System: ");
switch (ver) {
case SVR_8641:
if (SVR_SUBVER(svr) == 1) {
puts("8641D");
} else {
puts("8641");
}
break;
default:
puts("Unknown");
break;
}
printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
get_sys_info(&sysinfo);
puts(" Clocks: ");
printf("CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
printf("MPX:%4lu MHz, ", sysinfo.freqSystemBus / 1000000);
printf("DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
#if defined(CFG_LBC_LCRR)
lcrr = CFG_LBC_LCRR;
#else
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
lcrr = lbc->lcrr;
}
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);
} else {
printf(" LBC: unknown (lcrr: 0x%08x)\n", lcrr);
}
puts(" L2: ");
if (get_l2cr() & 0x80000000)
puts("Enabled\n");
else
puts("Disabled\n");
return 0;
}
int cpu_init_r(void)
{
#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
volatile immap_t *immap = (immap_t *)CFG_IMMR;
#endif
#ifdef CONFIG_CLEAR_LAW0
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
/* clear alternate boot location LAW (used for sdram, or ddr bank) */
ecm->lawar0 = 0;
#endif
#if defined(CONFIG_L2_CACHE)
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
volatile uint cache_ctl;
uint svr, ver;
uint l2srbar;
svr = get_svr();
ver = SVR_VER(svr);
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
switch (cache_ctl & 0x30000000) {
case 0x20000000:
if (ver == SVR_8548 || ver == SVR_8548_E ||
ver == SVR_8544 || ver == SVR_8568_E) {
printf ("L2 cache 512KB:");
/* set L2E=1, L2I=1, & L2SRAM=0 */
cache_ctl = 0xc0000000;
} else {
printf ("L2 cache 256KB:");
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
cache_ctl = 0xc8000000;
}
break;
case 0x10000000:
printf ("L2 cache 256KB:");
if (ver == SVR_8544 || ver == SVR_8544_E) {
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
}
break;
case 0x30000000:
case 0x00000000:
default:
printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
return -1;
}
if (l2cache->l2ctl & 0x80000000) {
printf(" already enabled.");
l2srbar = l2cache->l2srbar0;
#ifdef CFG_INIT_L2_ADDR
if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
l2srbar = CFG_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
}
#endif /* CFG_INIT_L2_ADDR */
puts("\n");
} else {
asm("msync;isync");
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
asm("msync;isync");
printf(" enabled\n");
}
#else
printf("L2 cache: disabled\n");
#endif
#ifdef CONFIG_QE
uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
qe_init(qe_base);
qe_reset();
#endif
return 0;
}
