t_stat sage_translateaddr(t_addr in,t_addr* out, IOHANDLER** ioh,int rw,int fc,int dma)
{
static uint32 bptype[] = { R_BKPT_SPC|SWMASK('R'), W_BKPT_SPC|SWMASK('W') };
t_addr ma = in & addrmask;
if (sim_brk_summ && sim_brk_test(ma, bptype[rw])) return STOP_IBKPT;
return m68k_translateaddr(in,out,ioh,rw,fc,dma);
}
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
t_stat r;
int32 val;
uint32 origin, limit;
if (flag) /* dump? */
return SCPE_ARG;
origin = 0; /* memory */
limit = (uint32) cpu_unit.capac;
if (sim_switches & SWMASK ('O')) { /* origin? */
origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
if (r != SCPE_OK)
return SCPE_ARG;
}
while ((val = getc (fileref)) != EOF) { /* read byte stream */
if (sim_switches & SWMASK ('R')) { /* ROM0? */
return SCPE_NXM;
}
else if (sim_switches & SWMASK ('S')) { /* ROM1? */
return SCPE_NXM;
}
else {
if (origin >= limit) /* NXM? */
return SCPE_NXM;
WriteB (origin, val); /* memory */
}
origin = origin + 1;
}
return SCPE_OK;
}
t_stat qty_attach( UNIT * unitp, char * cptr )
{
t_stat r ;
int a ;
/* switches: A auto-disconnect
* M modem control
*/
qty_mdm = qty_auto = 0; /* modem ctl off */
r = tmxr_attach( &qty_desc, unitp, cptr ) ; /* attach QTY */
if ( r != SCPE_OK )
{
return ( r ) ; /* error! */
}
if ( sim_switches & SWMASK('M') ) /* modem control? */
{
qty_mdm = 1;
sim_printf( "Modem control activated\n" ) ;
if ( sim_switches & SWMASK ('A') ) /* autodisconnect? */
{
qty_auto = 1 ;
sim_printf( "Auto disconnect activated\n" ) ;
}
}
qty_polls = 0 ;
for ( a = 0 ; a < QTY_MAX ; ++a )
{
/* QTY lines are always enabled - force RX and TX to 'enabled' */
qty_status[ a ] = (QTY_L_RXE | QTY_L_TXE) ;
}
sim_activate( unitp, tmxr_poll ) ;
return ( SCPE_OK ) ;
} /* end of 'qty_attach' */
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
if ((*cptr != 0) || (flag != 0))
return SCPE_ARG;
if ((sim_switches & SWMASK ('R')) || /* RIM format? */
(match_ext (fnam, "RIM") && !(sim_switches & SWMASK ('B'))))
return sim_load_rim (fileref);
else return sim_load_bin (fileref); /* no, BIN */
}
t_stat dp_setformat (UNIT *uptr, int32 val, char *cptr, void *desc)
{
uint32 h, c, cntr, rptr;
int32 i, nr, nw, inp;
uint16 tbuf[DP_TRKLEN];
float finp;
t_stat r;
if (uptr == NULL)
return SCPE_IERR;
if (cptr == NULL)
return SCPE_ARG;
if (!(uptr->flags & UNIT_ATT))
return SCPE_UNATT;
inp = (int32) get_uint (cptr, 10, 2048, &r);
if (r != SCPE_OK)
return r;
if (inp == 0)
return SCPE_ARG;
finp = (float) inp;
if (sim_switches & SWMASK ('R')) { /* format records? */
nr = inp;
nw = (int32) ((dp_tab[dp_ctype].wrds / (finp + ((finp - 1.0) / 20.0))) - REC_OVHD_WRDS);
if (nw <= 0)
return SCPE_ARG;
}
else {
nw = inp; /* format words */
nr = (int32) ((((20.0 * dp_tab[dp_ctype].wrds) / (finp + REC_OVHD_WRDS)) + 1.0) / 21.0);
if (nr <= 0)
return SCPE_ARG;
}
printf ("Proposed format: records/track = %d, record size = %d\n", nr, nw);
if (!get_yn ("Formatting will destroy all data on this disk; proceed? [N]", FALSE))
return SCPE_OK;
for (c = cntr = 0; c < dp_tab[dp_ctype].cyl; c++) {
for (h = 0; h < dp_tab[dp_ctype].surf; h++) {
for (i = 0; i < DP_TRKLEN; i++)
tbuf[i] = 0;
rptr = 0;
for (i = 0; i < nr; i++) {
tbuf[rptr + REC_LNT] = nw & DMASK;
if (sim_switches & SWMASK ('S'))
tbuf[rptr + REC_ADDR] = cntr++;
else tbuf[rptr + REC_ADDR] = (c << 8) + (h << 3) + i;
rptr = rptr + nw + REC_OVHD;
}
if (r = dp_wrtrk (uptr, tbuf, c, h))
return r;
}
}
printf ("Formatting complete\n");
return SCPE_OK;
}
t_stat dqc_reset (DEVICE *dptr)
{
int32 drv;
DIB *dibptr = (DIB *) dptr->ctxt; /* DIB pointer */
hp_enbdis_pair (dptr, /* make pair cons */
(dptr == &dqd_dev)? &dqc_dev: &dqd_dev);
if (sim_switches & SWMASK ('P')) { /* initialization reset? */
dqd_ibuf = 0; /* clear buffers */
dqd_obuf = 0;
dqc_obuf = 0; /* clear buffer */
dqc_rarc = dqc_rarh = dqc_rars = 0; /* clear RAR */
}
IOPRESET (dibptr); /* PRESET device (does not use PON) */
dqc_busy = 0; /* reset controller state */
dqd_xfer = 0;
dqd_wval = 0;
dq_ptr = 0;
sim_cancel (&dqd_unit); /* cancel dch */
for (drv = 0; drv < DQ_NUMDRV; drv++) { /* loop thru drives */
sim_cancel (&dqc_unit[drv]); /* cancel activity */
dqc_unit[drv].FNC = 0; /* clear function */
dqc_ucyl[drv] = dqc_uhed[drv] = 0; /* clear drive pos */
dqc_sta[drv] = 0; /* clear status */
}
return SCPE_OK;
}
t_stat m68kcpu_ex(t_value* eval_array, t_addr addr, UNIT* uptr, int32 sw)
{
uint32 val = 0;
t_stat rc = (sw & SWMASK('V')) ? ReadVW(addr,&val) : ReadPW(addr,&val);
if (rc==SCPE_OK) *eval_array = val;
return rc;
}
t_stat ptp_attach (UNIT *uptr, CONST char *cptr)
{
if (sim_switches & SWMASK ('A'))
uptr->flags = uptr->flags | UNIT_ASCII;
else uptr->flags = uptr->flags & ~UNIT_ASCII;
return attach_unit (uptr, cptr);
}
t_stat pt_attach (UNIT *uptr, char *cptr)
{
t_stat r;
if (!(uptr->flags & UNIT_ATTABLE))
return SCPE_NOFNC;
if (r = attach_unit (uptr, cptr))
return r;
if (sim_switches & SWMASK ('A')) /* -a? ASCII */
uptr->flags |= UNIT_ASC;
else if (sim_switches & SWMASK ('U')) /* -u? Unix ASCII */
uptr->flags |= (UNIT_ASC|UNIT_UASC);
else if (sim_switches & SWMASK ('B')) /* -b? binary */
uptr->flags &= ~(UNIT_ASC|UNIT_UASC);
uptr->STA = 0;
return r;
}
t_stat ptr_attach (UNIT *uptr, CONST char *cptr)
{
ptr_leader = PTR_LEADER; /* set up leader */
if (sim_switches & SWMASK ('A'))
uptr->flags = uptr->flags | UNIT_ASCII;
else uptr->flags = uptr->flags & ~UNIT_ASCII;
return attach_unit (uptr, cptr);
}
t_stat cd_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
r = attach_unit (uptr, cptr);
if (r != SCPE_OK) /* attach */
return r;
if (sim_switches & SWMASK ('T')) /* text? */
uptr->flags = uptr->flags & ~UNIT_CBN;
else if (sim_switches & SWMASK ('C')) /* column binary? */
uptr->flags = uptr->flags | UNIT_CBN;
else if (match_ext (cptr, "TXT")) /* .txt? */
uptr->flags = uptr->flags & ~UNIT_CBN;
else if (match_ext (cptr, "CBN")) /* .cbn? */
uptr->flags = uptr->flags | UNIT_CBN;
return SCPE_OK;
}
t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fname, int flag)
{
t_addr lo, hi;
if (flag == 0)
return SCPE_ARG;
/*
* We want to write the memory in some device-dependent format. sim_switches
* contains the command switches which will be used to determine the
* format:
*
* -p Paper tape format
*
* Command syntax is:
*
* dump <file> -p <loaddr>-<hiaddr>
*/
if ((sim_switches & SWMASK('P')) != 0) {
const char *tptr;
t_addr addr;
int temp, count = 0;
tptr = get_range(NULL, cptr, &lo, &hi, cpu_dev.aradix, cpu_unit.capac - 1, 0);
if (tptr != NULL) {
/*
* Output a couple of NULL frames to start the dump
*/
fputc(0, fileref);
fputc(0, fileref);
for (addr = lo; addr <= hi; addr++) {
temp = M[addr];
/*
* If the data is 0, map it to -0 (0xFFFF) since 0 terminates the
* sequence. We also count the number of times this happens and
* report it at the end.
*/
if (temp == 0) {
temp =0xFFFF;
count++;
}
fputc((temp >> 8) & 0xFF, fileref);
fputc(temp & 0xFF, fileref);
}
/*
* Terminate the dump with 2 more NULL frames
*/
fputc(0, fileref);
fputc(0, fileref);
if (count != 0)
printf("%d zero word translated to 0xFFFF\n", count);
return SCPE_OK;
}
}
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 cflag, cm, i, j, inst, disp;
uint32 irq;
cflag = (uptr == NULL) || (uptr == &cpu_unit);
inst = (int32) val[0];
if (sw & SWMASK ('A')) { /* ASCII? */
if (inst > 0377) return SCPE_ARG;
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK;
}
if (sw & SWMASK ('C')) { /* characters? */
fprintf (of, FMTASC ((inst >> 8) & 0177));
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK;
}
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
uint32 inst;
if (sw & SWMASK ('H')) return SCPE_ARG; /* hexadecimal? */
inst = val[0];
if (sw & SWMASK ('D')) /* decimal? */
return ssem_fprint_decimal(of, inst);
if (sw & SWMASK ('M')) { /* mnemomic? */
return ssem_fprint_competition_mnemonic(of, inst);
}
return ssem_fprint_binary(of, inst, sw & SWMASK ('I') || sw & SWMASK ('M'));
}
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
int32 i, j;
uint32 inst, src, dst, op, bop;
inst = val[0];
if (sw & SWMASK ('A')) { /* ASCII? */
if (inst > 0377)
return SCPE_ARG;
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK;
}
if (sw & SWMASK ('C')) { /* characters? */
fprintf (of, FMTASC ((inst >> 8) & 0177));
fprintf (of, FMTASC (inst & 0177));
return SCPE_OK;
}
/* Symbolic decode
Inputs:
*of = output stream
addr = current PC
*val = pointer to data
*uptr = pointer to unit
sw = switches
Outputs:
return = status code
*/
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw)
{
t_addr off;
T_FLCVT t;
int ch;
if (sw & SWMASK('M') && !ADDR_ISWORD(addr)) {
return fprint_sym_m(of, addr, val, uptr, sw);
}
if (sw & SWMASK('B')) { /* as BYTE */
if (ADDR_ISWORD(addr)) {
fprint_val(of, (val[0]>>8) & 0xff, cpu_dev.dradix, 8, PV_RZRO);
fprintf(of, ",");
fprint_val(of, val[0] & 0xff, cpu_dev.dradix, 8, PV_RZRO);
} else
fprint_val(of, val[0], cpu_dev.dradix, 8, PV_RZRO);
return SCPE_OK;
}
t_stat sim_instr (void)
{
t_stat r = 0;
uint32 oPC;
/* Restore register state */
PC = PC & AMASK; /* mask PC */
sim_cancel_step (); /* defang SCP step */
if (lgp21_sov) { /* stop sense pending? */
lgp21_sov = 0;
if (!OVF) /* ovf off? skip */
PC = (PC + 1) & AMASK;
else OVF = 0; /* on? reset */
}
/* Main instruction fetch/decode loop */
do {
if (sim_interval <= 0) { /* check clock queue */
if ((r = sim_process_event ()))
break;
}
if (delay > 0) { /* delay to next instr */
delay = delay - 1; /* count down delay */
sim_interval = sim_interval - 1;
continue; /* skip execution */
}
if (sim_brk_summ && /* breakpoint? */
sim_brk_test (PC, SWMASK ('E'))) {
r = STOP_IBKPT; /* stop simulation */
break;
}
IR = Read (oPC = PC); /* get instruction */
PC = (PC + 1) & AMASK; /* increment PC */
sim_interval = sim_interval - 1;
if ((r = cpu_one_inst (oPC, IR))) { /* one instr; error? */
if (r == STOP_STALL) { /* stall? */
PC = oPC; /* back up PC */
delay = r = 0; /* no delay */
}
else break;
}
if (sim_step && (--sim_step <= 0)) /* do step count */
r = SCPE_STOP;
} while (r == 0); /* loop until halted */
pcq_r->qptr = pcq_p; /* update pc q ptr */
return r;
}
/*
* Special address print routine for "Relative" display.
*/
static void sprintAddress(char *buf, DEVICE *dptr, t_addr addr)
{
if ((dptr == sim_devices[0]) && ((sim_switches & SWMASK('R')) != 0)) {
if (!RelValid) {
RelBase = (uint16)addr;
RelValid = TRUE;
}
addr -= RelBase;
}
sprint_val(buf, addr, dptr->aradix, dptr->awidth, PV_RZRO);
}
t_stat clk_reset (DEVICE *dptr)
{
if (sim_switches & SWMASK ('P')) { /* initialization reset? */
clk_error = 0; /* clear error */
clk_select = 0; /* clear select */
clk_ctr = 0; /* clear counter */
}
IOPRESET (&clk_dib); /* PRESET device (does not use PON) */
return SCPE_OK;
}
t_stat mt_boot (int32 unitno, DEVICE *dptr)
{
extern int32 saved_IS;
extern int32 sim_switches;
if ((sim_switches & SWMASK ('N')) == 0) /* unless -n */
sim_tape_rewind (&mt_unit[unitno]); /* force rewind */
BS = 1; /* set BS = 001 */
mt_io (unitno, MD_WM + MD_BOOT, BCD_R); /* LDA %U1 001 R */
saved_IS = 1;
return SCPE_OK;
}
t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
{
if (sw & SWMASK ('H')) return SCPE_ARG; /* hexadecimal? */
while (isspace (*cptr)) cptr++; /* absorb spaces */
if (sw & SWMASK ('D')) { /* decimal? */
return parse_sym_d (cptr, val);
}
if (sw & SWMASK ('I')) { /* backward binary instruction? */
return parse_sym_i (cptr, val);
}
if (sw & SWMASK ('M')) { /* mnemonic? */
return parse_sym_m (cptr, val);
}
return parse_sym_b(cptr, val); /* backward binary number */
}
t_stat tty_reset (DEVICE *dptr)
{
if (sim_switches & SWMASK ('P')) /* initialization reset? */
tty_buf = 0; /* clear buffer */
IOPRESET (&tty_dib); /* PRESET device (does not use PON) */
tty_unit[TTI].wait = POLL_WAIT; /* reset initial poll */
sim_rtcn_init (tty_unit[TTI].wait, TMR_POLL); /* init poll timer */
sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* activate poll */
sim_cancel (&tty_unit[TTO]); /* cancel output */
return SCPE_OK;
}
t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag)
{
t_stat r;
int32 i;
uint32 origin, limit;
extern int32 ssc_cnf;
#define SSCCNF_BLO 0x80000000
if (flag) /* dump? */
return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n");
if (sim_switches & SWMASK ('R')) { /* ROM? */
origin = ROMBASE;
limit = ROMBASE + ROMSIZE;
}
else if (sim_switches & SWMASK ('N')) { /* NVR? */
origin = NVRBASE;
limit = NVRBASE + NVRSIZE;
ssc_cnf = ssc_cnf & ~SSCCNF_BLO;
}
else {
origin = 0; /* memory */
limit = (uint32) cpu_unit.capac;
if (sim_switches & SWMASK ('O')) { /* origin? */
origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
if (r != SCPE_OK)
return SCPE_ARG;
}
}
while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */
if (origin >= limit) /* NXM? */
return SCPE_NXM;
if (sim_switches & SWMASK ('R')) /* ROM? */
rom_wr_B (origin, i); /* not writeable */
else WriteB (origin, i); /* store byte */
origin = origin + 1;
}
return SCPE_OK;
}
t_stat sim_load_bin (FILE *fi)
{
int32 hi, lo, wd, csum, t;
uint32 field, newf, origin;
int32 sections_read = 0;
for (;;) {
csum = origin = field = newf = 0; /* init */
do { /* skip leader */
if ((hi = sim_bin_getc (fi, &newf)) == EOF) {
if (sections_read != 0) {
sim_printf ("%d sections sucessfully read\n\r", sections_read);
return SCPE_OK;
}
else
return SCPE_FMT;
}
} while ((hi == 0) || (hi >= 0200));
for (;;) { /* data blocks */
if ((lo = sim_bin_getc (fi, &newf)) == EOF) /* low char */
return SCPE_FMT;
wd = (hi << 6) | lo; /* form word */
t = hi; /* save for csum */
if ((hi = sim_bin_getc (fi, &newf)) == EOF) /* next char */
return SCPE_FMT;
if (hi == 0200) { /* end of tape? */
if ((csum - wd) & 07777) { /* valid csum? */
if (sections_read != 0)
sim_printf ("%d sections sucessfully read\n\r", sections_read);
return SCPE_CSUM;
}
if (!(sim_switches & SWMASK ('A'))) /* Load all sections? */
return SCPE_OK;
sections_read++;
break;
}
csum = csum + t + lo; /* add to csum */
if (wd > 07777) /* chan 7 set? */
origin = wd & 07777; /* new origin */
else { /* no, data */
if ((field | origin) >= MEMSIZE)
return SCPE_NXM;
M[field | origin] = wd;
origin = (origin + 1) & 07777;
}
field = newf; /* update field */
}
}
return SCPE_IERR;
}
t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
{
int32 cflag, ch, OP, F, TAG, INDIR, DSPLC, IR, eaddr;
char *mnem, tst[12];
cflag = (uptr == NULL) || (uptr == &cpu_unit);
/* if (sw & SWMASK ('A')) { // ASCII? not useful
fprintf (of, (c1 < 040)? "<%03o>": "%c", c1);
return SCPE_OK;
}
*/
if (sw & SWMASK ('C')) /* character? not useful -- make it EBCDIC */
sw |= SWMASK('E');
if (sw & SWMASK ('E')) { /* EBCDIC! */
ch = ebcdic_to_ascii((val[0] >> 8) & 0xFF); /* take high byte first */
fprintf (of, (ch < ' ')? "<%03o>": "%c", ch);
ch = ebcdic_to_ascii(val[0] & 0xFF);
fprintf (of, (ch < ' ')? "<%03o>": "%c", ch);
return SCPE_OK;
}
t_stat clk_reset (DEVICE *dptr)
{
if (sim_switches & SWMASK ('P')) { /* initialization reset? */
clk_error = 0; /* clear error */
clk_select = 0; /* clear select */
clk_ctr = 0; /* clear counter */
if (clk_dev.lname == NULL) /* logical name unassigned? */
clk_dev.lname = strdup ("TBG"); /* allocate and initialize the name */
}
IOPRESET (&clk_dib); /* PRESET device (does not use PON) */
return SCPE_OK;
}
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
t_stat r;
int32 i;
uint32 origin, limit, step = 1;
if (flag) /* dump? */
return SCPE_ARG;
if (sim_switches & SWMASK ('R')) { /* ROM? */
origin = ROMBASE;
limit = ROMBASE + ROMSIZE;
}
else if (sim_switches & SWMASK ('N')) { /* NVR? */
origin = NVRBASE;
limit = NVRBASE + NVRASIZE;
step = 2;
}
else {
origin = 0; /* memory */
limit = (uint32) cpu_unit.capac;
if (sim_switches & SWMASK ('O')) { /* origin? */
origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
if (r != SCPE_OK)
return SCPE_ARG;
}
}
while ((i = getc (fileref)) != EOF) { /* read byte stream */
if (origin >= limit) /* NXM? */
return SCPE_NXM;
if (sim_switches & SWMASK ('R')) /* ROM? */
rom_wr_B (origin, i); /* not writeable */
else WriteB (origin, i); /* store byte */
origin = origin + step;
}
return SCPE_OK;
}
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
t_stat r;
int32 val;
uint32 origin, limit;
if (flag) /* dump? */
return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n");
origin = 0; /* memory */
limit = (uint32) cpu_unit.capac;
if (sim_switches & SWMASK ('O')) { /* origin? */
origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
if (r != SCPE_OK)
return SCPE_ARG;
}
while ((val = Fgetc (fileref)) != EOF) { /* read byte stream */
if (sim_switches & SWMASK ('R')) { /* ROM0? */
if (origin >= ROMSIZE)
return SCPE_NXM;
rom_wr_B (ROM0BASE + origin, val);
}
else if (sim_switches & SWMASK ('S')) { /* ROM1? */
if (origin >= ROMSIZE)
return SCPE_NXM;
rom_wr_B (ROM1BASE + origin, val);
}
else {
if (origin >= limit) /* NXM? */
return SCPE_NXM;
WriteB (origin, val); /* memory */
}
origin = origin + 1;
}
return SCPE_OK;
}
t_stat
fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw)
{
t_value inst = *val;
int i;
fputc(' ', of);
fprint_val(of, inst, 8, 48, PV_RZRO);
if (sw & SWMASK('W')) { /* Word mode opcodes */
fputs(" ", of);
for (i = 36; i >= 0; i-=12) {
int op = (int)(inst >> i) & 07777;
print_opcode(of, op, word_ops);
}
}
t_stat sim_instr (void)
{
t_stat reason = 0;
sim_cancel_step (); /* defang SCP step */
/* Main instruction fetch/decode loop */
do {
if (sim_interval <= 0) { /* check clock queue */
#if !UNIX_PLATFORM
if ((reason = sim_poll_kbd()) == SCPE_STOP) { /* poll on platforms without reliable signalling */
break;
}
#endif
if ((reason = sim_process_event ()))
break;
}
if (sim_brk_summ && /* breakpoint? */
sim_brk_test (*C, SWMASK ('E'))) {
reason = STOP_IBKPT; /* stop simulation */
break;
}
/* Increment current instruction */
*C = (*C + 1) & AMASK;
/* Get present instruction */
C[1] = Read (*C);
Staticisor = C[1] & IMASK; /* get instruction */
sim_interval = sim_interval - 1;
if ((reason = cpu_one_inst (*C, Staticisor))) { /* one instr; error? */
break;
}
if (sim_step && (--sim_step <= 0)) /* do step count */
reason = SCPE_STOP;
} while (reason == 0); /* loop until halted */
return reason;
}
