bool SrSetAnt(HANDLE hCom, unsigned char cAntMask, unsigned int *pdwErr) {
int ret = SetAnt(hCom, cAntMask, pdwErr);
if (ret == -1) {
*pdwErr = ERR_CODE_SET_ANT;
return false;
}
return true;
}
void SetupRecieveTestPacket( U8 radio )
{
SetAnt( radio, ANT_RX );
msleep( 50 );
WriteRegister( radio, RFREG_FUNC_CTRL_1, xton ); // to ready mode
//clear interrupts.
ReadRegister( radio, RFREG_INT_STATUS_1);
ReadRegister( radio, RFREG_INT_STATUS_2);
WriteRegister( radio, RFREG_RX_FIFO_CTRL, 17);//rx fifo almost full threshold set to 17.
WriteRegister( radio, RFREG_FUNC_CTRL_2, 0x03);//clear both fifos
WriteRegister( radio, RFREG_FUNC_CTRL_2, 0x00);//second write in above opperation
WriteRegister( radio, RFREG_INT_EN_1, 2);//enable interrupt for valid packet received
WriteRegister( radio, RFREG_FUNC_CTRL_1, rxon | xton );//RX on in manual receiver mode. auto clears when a valid packet is received. (does nothing in multiple packet config)
//ready mode
}
void SentTestPacket( U8 radio )
{
U8 i;
WriteRegister( radio, RFREG_FUNC_CTRL_1, xton); // To ready mode
SetAnt( radio, ANT_TX );
msleep( 50 );
WriteRegister( radio, RFREG_FUNC_CTRL_2, 0x03 ); // FIFO reset
WriteRegister( radio, RFREG_FUNC_CTRL_2, 0x00 ); // Clear FIFO
WriteRegister(radio, RFREG_PREAMBLE_LEN, 64); // preamble = 64nibble
WriteRegister(radio, RFREG_TX_PACKET_LEN, 17); // packet length = 17bytes
WriteRegister(radio, RFREG_FIFO_ACCESS, 'h');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'e');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'l');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'l');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'o');
WriteRegister(radio, RFREG_FIFO_ACCESS, ' ');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'w');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'o');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'r');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'l');
WriteRegister(radio, RFREG_FIFO_ACCESS, 'd');
WriteRegister(radio, RFREG_FIFO_ACCESS, '!');
WriteRegister(radio, RFREG_FIFO_ACCESS, ' ');
WriteRegister(radio, RFREG_FIFO_ACCESS, ' ');
WriteRegister(radio, RFREG_FIFO_ACCESS, ' ');
WriteRegister(radio, RFREG_FIFO_ACCESS, '1');
WriteRegister(radio, RFREG_FIFO_ACCESS, '7');
//for (i=0; i<17; i++)
//{
//WriteRegister(radio, RFREG_FIFO_ACCESS, 'h'); // send payload to the FIFO
//}
WriteRegister(radio, RFREG_INT_EN_1, 0x04); // enable packet sent interrupt
i = ReadRegister(radio, RFREG_INT_STATUS_1); // Read Interrupt status1 register
i = ReadRegister(radio, RFREG_INT_STATUS_2);
WriteRegister(radio, RFREG_FUNC_CTRL_1, txon | xton ); // Start TX
//while ((PIND & (1<<NIRQ)) != 0); // need to check interrupt here
//wait for Packet Sent interrupt to be set.
//wait up to 500ms, 10 ms at a time.
for( i=0; i < 50; ++i )
{
U8 status;
msleep( 10 ); //10ms
status = ReadRegister( radio, RFREG_INT_STATUS_1 );
if( ( status & (1 << 2) ) != 0 )
break;
}
//__delay_cycles( 100000 * 8 );
WriteRegister(radio, RFREG_FUNC_CTRL_1, xton ); // to ready mode
SetAnt( radio, ANT_OFF );
}
