TextureCache::TCacheEntryBase* TextureCache::CreateRenderTargetTexture(
unsigned int scaled_tex_w, unsigned int scaled_tex_h)
{
TCacheEntry *const entry = new TCacheEntry;
glActiveTexture(GL_TEXTURE0+9);
glBindTexture(GL_TEXTURE_2D, entry->texture);
GL_REPORT_ERRORD();
const GLenum
gl_format = GL_RGBA,
gl_iformat = GL_RGBA,
gl_type = GL_UNSIGNED_BYTE;
glTexParameteri(GL_TEXTURE_2D, GL_TEXTURE_MAX_LEVEL, 0);
glTexImage2D(GL_TEXTURE_2D, 0, gl_iformat, scaled_tex_w, scaled_tex_h, 0, gl_format, gl_type, nullptr);
glBindTexture(GL_TEXTURE_2D, 0);
glGenFramebuffers(1, &entry->framebuffer);
FramebufferManager::SetFramebuffer(entry->framebuffer);
glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_2D, entry->texture, 0);
GL_REPORT_FBO_ERROR();
SetStage();
GL_REPORT_ERRORD();
return entry;
}
void Board::Init() {
for (int y = 0; y < kStageHeight; y++) {
for (int x = 0; x < kStageWidth; x++) {
stage[y][x] = -1;
}
}
SetStage(MSSMSMSM); // 한:마상상마, 초:상마상마
}
int PanelSDK::KeybEvent(DWORD key,char *kstate)
{
KeyPress *runner;
runner=VESSELMGMT->DefinedKeys;
while ((runner)&&(runner->key!=key))
runner=runner->next;
if (runner)
if (runner->trigger_type==1)
SetStage(runner->index,0); //separate
return 0;
}
void NetworkPage::TestWinFirewall()
{
TCHAR l_app_path[MAX_PATH];
l_app_path[0] = 0;
::GetModuleFileName(NULL, l_app_path, MAX_PATH);
#ifdef FLYLINKDC_USE_SSA_WINFIREWALL
bool l_res = false;
try
{
l_res = WinFirewall::IsWindowsFirewallAppEnabled(l_app_path) != FALSE;
}
catch (...)
{
}
bool authorized = l_res;
#else
talk_base::WinFirewall fw;
HRESULT hr = {0};
bool authorized;
fw.Initialize(&hr);
const auto l_res = fw.QueryAuthorizedW(l_app_path, &authorized);
#endif
if (l_res)
{
if (authorized)
{
SetStage(IDC_NETWORK_WINFIREWALL_ICO, StageSuccess);
}
else
{
SetStage(IDC_NETWORK_WINFIREWALL_ICO, StageFail);
}
}
else
{
SetStage(IDC_NETWORK_WINFIREWALL_ICO, StageQuestion);
}
}
usa_InputFile::usa_InputFile( const char* file, int id, int id_serv, int file_class, size_t file_groups, int file_status,int origin_file_status, int file_part) :
gfr_Msg( file_class),
_error_code(0),
_file_groups(file_groups),
_file_id(id),
_file_id_serv(id_serv),
_file_name(file),
_file_part(file_part),
_file_status(file_status),
_origin_file_status(origin_file_status),//KBSqa17086
_processed(0),
_processingStarted(false),
_recs_DUC(0),
_recs_DUP(0),
_recs_TAX(0),
_recs_WTAX(0),
_sizeProblem(false),
_start_group_admin(0),
_start_group_cust(0),
_status(PROCESSING),
_total_DUC(0),
_total_DUP(0),
_total_TAX(0),
_total_WTAX(0),
_type(NULL)
{
SetRecords(1);
SetStage(1);
if ( !gfr_FileTypeMgr::Instance()->FindByType( _type, file_class))
{
THROWGFREXCEPTION1( GFR_GENERIC_DEBUG, "invalid file_class %1", GFRSEV_ERROR, file_class)
}
SetType( _type->FileType().AsInt());
_type_batch.resize( GFR_DATA_TYPE_MGR::Mgr().TypeCount());
std::fill( _type_batch.begin(), _type_batch.end(), 0);
_type_totals.resize( GFR_DATA_TYPE_MGR::Mgr().TypeCount());
std::fill( _type_totals.begin(), _type_totals.end(), 0);
_recs_batch.resize( GFR_DATA_TYPE_MGR::Mgr().TypeCount());
std::fill( _recs_batch.begin(), _recs_batch.end(), 0);
_recs_totals.resize( GFR_DATA_TYPE_MGR::Mgr().TypeCount());
std::fill( _recs_totals.begin(), _recs_totals.end(), 0);
}
void NetworkPage::updateTestPortIcon(bool p_is_wait)
{
//if (::IsWindow(m_BindCombo))
{
if (!p_is_wait)
{
++m_count_test_port_tick;
}
auto calcIconsIndex = [&](const int p_icon, const boost::logic::tribool & p_status)
{
if (p_is_wait && m_count_test_port_tick == 0)
{
SetStage(p_icon, StageWait);
}
else if (p_status)
{
SetStage(p_icon, StageSuccess);
}
else if (!p_status) // || (m_count_test_port_tick > 1 && boost::logic::indeterminate(p_status))
{
SetStage(p_icon, StageFail);
}
else
{
SetStage(p_icon, StageQuestion);
}
};
calcIconsIndex(IDC_NETWORK_TEST_PORT_TCP_ICO, SettingsManager::g_TestTCPLevel);
calcIconsIndex(IDC_NETWORK_TEST_PORT_UDP_ICO, SettingsManager::g_TestUDPSearchLevel);
if (CryptoManager::getInstance()->TLSOk())
{
calcIconsIndex(IDC_NETWORK_TEST_PORT_TLS_TCP_ICO, SettingsManager::g_TestTSLLevel);
}
else
{
SetStage(IDC_NETWORK_TEST_PORT_TLS_TCP_ICO, StageUnknown);
}
const BOOL dht = IsDlgButtonChecked(IDC_SETTINGS_USE_DHT) == BST_CHECKED;
if (dht)
{
calcIconsIndex(IDC_NETWORK_TEST_PORT_DHT_UDP_ICO, SettingsManager::g_TestUDPDHTLevel);
}
else
{
SetStage(IDC_NETWORK_TEST_PORT_DHT_UDP_ICO, StageUnknown);
}
}
}
void CStageLine::StageInit
(BoxDirection a_eBoxDirection, Layer * a_pParentLayer,
int a_nStageNum, Vec2 a_Position)
{
m_eBoxDirection = a_eBoxDirection;
m_nStagenum = a_nStageNum;
m_pParentLayer = a_pParentLayer;
m_Position = a_Position;
for (int i = 0; i < 10; i++)
{
m_pStage[i] = Sprite::create();
a_pParentLayer->addChild(m_pStage[i],2);
}
SetStage();
switch (a_eBoxDirection)
{
case BoxDirection::Left:
LeftBoxStageCreator();
break;
case BoxDirection::Down:
DownBoxStageCreator();
break;
case BoxDirection::Right:
RightBoxStageCreator();
break;
default:
break;
}
m_vLines[0]->setWork(true);
}
void EjectedPilotClass::AdvanceTime()
{
// Get delta time.
_deltaTime =
(
_stage == PD_START ?
0.0F :
SimLibMajorFrameTime
);
// Update position.
//XX _pos += _vel * _deltaTime;
EP_VECTOR p;
p = _vel;
p *= _deltaTime;
_pos += p;
// Update orientation.
// Set roll velocity to -roll angle, tilt back towards the sun
// Set pitch velocity to -pitch angle, tilt back towards the sun
_aVel[I_PITCH] = -_rot[I_PITCH]*1.5F;
_aVel[I_ROLL] = -_rot[I_ROLL]*1.5F;
//XX _rot += _aVel * _deltaTime;
p = _aVel;
p *= _deltaTime;
_rot += p;
//MonoPrint ("Pitch %.2f rate %.2f\n", _rot[I_PITCH]*RTD, _aVel[I_PITCH]*RTD);
// Increment total run time.
_runTime += _deltaTime;
// Advance stage if necessary.
if(!_hitGround && _collapseChute && _stage != PD_FREE_FALL_WITH_COLLAPSED_CHUTE)
{
SetStage(PD_FREE_FALL_WITH_COLLAPSED_CHUTE);
InitFreeFallWithCollapsedChute();
}
// advance when ground has been hit
else if ( _hitGround )
{
if ( _stage < PD_SAFE_LANDING )
{
// only open chute results in safe landing
if ( _stage == PD_FREE_FALL_WITH_OPEN_CHUTE )
{
SetStage(PD_SAFE_LANDING);
InitSafeLanding();
}
else
{
SetStage(PD_CRASH_LANDING);
InitCrashLanding();
}
}
}
else
{
while(_stage < PD_FREE_FALL_WITH_OPEN_CHUTE && _runTime >= StageEndTime())
{
switch(AdvanceStage())
{
case PD_JETTISON_CANOPY :
{
InitJettisonCanopy();
break;
}
case PD_EJECT_SEAT :
{
InitEjectSeat();
break;
}
case PD_FREE_FALL_WITH_SEAT :
{
InitFreeFallWithSeat();
break;
}
case PD_CHUTE_OPENING :
{
InitChuteOpening();
break;
}
case PD_FREE_FALL_WITH_OPEN_CHUTE :
{
InitFreeFallWithOpenChute();
break;
}
default :
{
ShiWarning ("Bad Eject Mode");
}
}
}
#if DEBUG_EJECTION_SEQUENCE
SpewDebugData();
#endif // DEBUG_EJECTION_SEQUENCE
}
}
void SetEffect (Effect* effect)
{
_effect = effect;
SetStage(0);
}
//**************************************************************************
void
control_inst_t::Retire( abstract_pc_t *a )
{
#ifdef DEBUG_DYNAMIC_RET
DEBUG_OUT("control_inst_t:Retire BEGIN, proc[%d]\n",m_proc);
#endif
#ifdef DEBUG_DYNAMIC
char buf[128];
s->printDisassemble(buf);
DEBUG_OUT("\tcontrol_inst_t::Retire BEGIN %s seq_num[ %lld ] cycle[ %lld ] fetchPC[ 0x%llx ] fetchNPC[ 0x%llx ] PredictedPC[ 0x%llx ] PredictedNPC[ 0x%llx ]\n", buf, seq_num, m_pseq->getLocalCycle(), m_actual.pc, m_actual.npc, m_predicted.pc, m_predicted.npc);
for(int i=0; i < SI_MAX_DEST; ++i){
reg_id_t & dest = getDestReg(i);
reg_id_t & tofree = getToFreeReg(i);
if( !dest.isZero() ){
DEBUG_OUT("\tDest[ %d ] Vanilla[ %d ] Physical[ %d ] Arf[ %s ] ToFree: Vanilla[ %d ] physical[ %d ] Arf[ %s ]\n", i, dest.getVanilla(), dest.getPhysical(), dest.rid_type_menomic( dest.getRtype() ), tofree.getVanilla(), tofree.getPhysical(), tofree.rid_type_menomic( tofree.getRtype() ) );
}
}
#endif
ASSERT( !getEvent( EVENT_FINALIZED ) );
STAT_INC( m_pseq->m_stat_control_retired[m_proc] );
// Need this bc we place fetch barrier on retry instead of stxa:
if ( (s->getOpcode() == i_retry) || (s->getFlag( SI_FETCH_BARRIER)) ) {
// if we have a branch misprediction, we already unstalled the fetch in partialSquash():
if(getEvent(EVENT_BRANCH_MISPREDICT) == false){
m_pseq->unstallFetch(m_proc);
}
}
STAT_INC( m_pseq->m_branch_seen_stat[s->getBranchType()][2] );
STAT_INC( m_pseq->m_branch_seen_stat[s->getBranchType()][m_priv? 1:0] );
// record when execution takes place
m_event_times[EVENT_TIME_RETIRE] = m_pseq->getLocalCycle() - m_fetch_cycle;
// update dynamic branch prediction (predicated) instruction statistics
static_inst_t *s_instr = getStaticInst();
if (s_instr->getType() == DYN_CONTROL) {
uint32 inst;
int op2;
int pred;
switch (s_instr->getBranchType()) {
case BRANCH_COND:
// conditional branch
STAT_INC( m_pseq->m_nonpred_retire_count_stat[m_proc] );
break;
case BRANCH_PCOND:
// predictated conditional
inst = s_instr->getInst();
op2 = maskBits32( inst, 22, 24 );
pred = maskBits32( inst, 19, 19 );
if ( op2 == 3 ) {
// integer register w/ predication
STAT_INC( m_pseq->m_pred_reg_retire_count_stat[m_proc] );
if (pred) {
STAT_INC( m_pseq->m_pred_reg_retire_taken_stat[m_proc] );
} else {
STAT_INC( m_pseq->m_pred_reg_retire_nottaken_stat[m_proc] );
}
} else {
STAT_INC( m_pseq->m_pred_retire_count_stat[m_proc] );
if (pred) {
STAT_INC( m_pseq->m_pred_retire_count_taken_stat[m_proc] );
} else {
STAT_INC( m_pseq->m_pred_retire_count_nottaken_stat[m_proc] );
}
}
if (pred == true && m_isTaken == false ||
pred == false && m_isTaken == true) {
STAT_INC( m_pseq->m_branch_wrong_static_stat );
}
break;
default:
; // ignore non-predictated branches
}
}
#ifdef DEBUG_RETIRE
m_pseq->out_info("## Control Retire Stage\n");
printDetail();
m_pseq->printPC( &m_actual );
#endif
bool mispredict = (m_events & EVENT_BRANCH_MISPREDICT);
if (mispredict) {
// incorrect branch prediction
STAT_INC( m_pseq->m_branch_wrong_stat[s->getBranchType()][2] );
STAT_INC( m_pseq->m_branch_wrong_stat[s->getBranchType()][m_priv? 1:0] );
//train BRANCH_PRIV predictor
if( (s->getBranchType() == BRANCH_PRIV) ){
if (m_predicted.cwp != m_actual.cwp) {
m_pseq->getRegstatePred()->update(getVPC(), CONTROL_CWP, m_actual.cwp, m_predicted.cwp);
}
if (m_predicted.tl != m_actual.tl) {
m_pseq->getRegstatePred()->update(getVPC(), CONTROL_TL, m_actual.tl, m_predicted.tl);
}
if (m_predicted.pstate != m_actual.pstate) {
m_pseq->getRegstatePred()->update(getVPC(), CONTROL_PSTATE, m_actual.pstate, m_predicted.pstate);
}
}
//****************************** print out mispredicted inst *****************
if(s->getBranchType() == BRANCH_PRIV){
char buf[128];
s->printDisassemble( buf );
bool imm = s->getFlag(SI_ISIMMEDIATE);
#if 0
if(m_predicted.pc != m_actual.pc){
m_pseq->out_info("CONTROLOP: PC mispredict: predicted[ 0x%llx ] actual[ 0x%llx ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] imm[ %d ] %s\n",
m_predicted.pc, m_actual.pc, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, imm, buf);
}
#endif
#if 0
if(m_predicted.npc != m_actual.npc){
m_pseq->out_info("CONTROLOP: NPC mispredict: predicted[ 0x%llx ] actual[ 0x%llx ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] imm[ %d ] %s\n",
m_predicted.npc, m_actual.npc, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, imm, buf);
}
#endif
#if 0
if (m_predicted.cwp != m_actual.cwp) {
m_pseq->out_info("CONTROLOP: CWP mispredict: predicted[ %d ] actual[ %d ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] imm[ %d ] %s\n",
m_predicted.cwp, m_actual.cwp, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, imm, buf);
}
#endif
#if 0
if (m_predicted.tl != m_actual.tl) {
m_pseq->out_info("CONTROLOP: TL mispredict: predicted[ %d ] actual[ %d ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] imm[ %d ] %s\n",
m_predicted.tl, m_actual.tl, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, imm, buf);
}
#endif
#if 0
if (m_predicted.pstate != m_actual.pstate) {
m_pseq->out_info("CONTROLOP: PSTATE mispredict: predicted[ 0x%0x ] actual[ 0x%0x ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] imm[ %d ] %s\n",
m_predicted.pstate, m_actual.pstate, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, imm, buf);
}
#endif
}
//**************************************************************************
// train ras's exception table
if (ras_t::EXCEPTION_TABLE && s->getBranchType() == BRANCH_RETURN) {
my_addr_t tos;
ras_t *ras = m_pseq->getRAS(m_proc);
ras->getTop(&(m_pred_state.ras_state), &tos);
if(tos == m_actual.npc) {
ras->markException(m_predicted.npc);
// update RAS state
ras->pop(&(m_pred_state.ras_state));
m_pseq->setSpecBPS(m_pred_state);
if (ras_t::DEBUG_RAS) m_pseq->out_info("*********** DEBUG_RAS ***********\n");
} else {
ras->unmarkException(m_actual.npc);
}
}
// XU DEBUG
if (0 && s->getBranchType() == BRANCH_RETURN) {
m_pseq->out_info("**** %c:mispred 0x%llx, pred 0x%llx target 0x%llx, "
"next %d TOS %d\n", m_priv? 'K':'U', getVPC(),
m_predicted.npc, m_actual.npc,
m_pred_state.ras_state.next_free,
m_pred_state.ras_state.TOS);
// print 5 instr after mis-pred
generic_address_t addr = m_predicted.npc-8;
for(uint32 i = 0; i < 5; i++, addr+=4) {
//get the actual seq number for the pointer to m_state:
int32 seq_num = m_pseq->getID() / CONFIG_LOGICAL_PER_PHY_PROC;
assert(seq_num >= 0 && seq_num < system_t::inst->m_numSMTProcs);
tuple_int_string_t *disassemble = SIM_disassemble((processor_t *) system_t::inst->m_state[seq_num]->getSimicsProcessor(m_proc), addr, /* logical */ 1);
if (disassemble) m_pseq->out_info(" %s\n", disassemble->string);
}
}
} else {
// correct or no prediction
STAT_INC( m_pseq->m_branch_right_stat[s->getBranchType()][2] );
STAT_INC( m_pseq->m_branch_right_stat[s->getBranchType()][m_priv? 1:0] );
}
/* update branch predictor tables at retirement */
if (s->getBranchType() == BRANCH_COND ||
s->getBranchType() == BRANCH_PCOND) {
m_pseq->getDirectBP()->Update(getVPC(),
(m_pseq->getArchBPS()->cond_state),
s->getFlag( SI_STATICPRED ),
m_isTaken, m_proc);
} else if (s->getBranchType() == BRANCH_INDIRECT ||
(s->getBranchType() == BRANCH_CALL && s->getOpcode() != i_call) ) {
// m_actual.npc is the indirect target
m_pseq->getIndirectBP()->Update( getVPC(),
&(m_pseq->getArchBPS()->indirect_state),
m_actual.npc, m_proc );
}
m_pseq->setArchBPS(m_pred_state);
// no need to update call&return, since we used checkpointed RAS
// no update on traps right now
SetStage(RETIRE_STAGE);
/* retire any register overwritten by link register */
retireRegisters();
#if 0
if(m_actual.pc == (my_addr_t) -1){
char buf[128];
s->printDisassemble(buf);
ERROR_OUT("\tcontrol_inst_t::Retire %s seq_num[ %lld ] cycle[ %lld ] fetchPC[ 0x%llx ] fetchNPC[ 0x%llx ] fetched[ %lld ] executed[ %lld ]\n", buf, seq_num, m_pseq->getLocalCycle(), m_actual.pc, m_actual.npc, m_fetch_cycle, m_fetch_cycle+getEventTime(EVENT_TIME_EXECUTE_DONE));
//print out writer cycle
for(int i=0; i < SI_MAX_SOURCE; ++i){
reg_id_t & source = getSourceReg(i);
if(!source.isZero()){
uint64 written_cycle = source.getARF()->getWrittenCycle( source, m_proc );
uint64 writer_seqnum = source.getARF()->getWriterSeqnum( source, m_proc );
ERROR_OUT("\tSource[ %d ] Vanilla[ %d ] Physical[ %d ] Arf[ %s ] written_cycle[ %lld ] writer_seqnum[ %lld ]\n", i, source.getVanilla(), source.getPhysical(), source.rid_type_menomic( source.getRtype() ), written_cycle, writer_seqnum);
}
}
}
#endif
ASSERT( m_actual.pc != (my_addr_t) -1 );
/* return pc, npc pair which are the results of execution */
a->pc = m_actual.pc;
a->npc = m_actual.npc;
markEvent( EVENT_FINALIZED );
#ifdef DEBUG_DYNAMIC_RET
DEBUG_OUT("control_inst_t:Retire END, proc[%d]\n",m_proc);
#endif
}
//**************************************************************************
void
control_inst_t::Execute()
{
STAT_INC( m_pseq->m_stat_control_exec[m_proc] );
m_event_times[EVENT_TIME_EXECUTE_DONE] = m_pseq->getLocalCycle() - m_fetch_cycle;
// call the appropriate function
static_inst_t *si = getStaticInst();
char buf[128];
s->printDisassemble(buf);
if (true) {
#ifdef DEBUG_DYNAMIC
char buf[128];
s->printDisassemble(buf);
DEBUG_OUT("[ %d ] control_inst_t: EXECUTE %s NAV[ %d ] seqnum[ %lld ] fetched[ %lld ] cycle[ %lld ]", m_pseq->getID(), buf, getInstrNAV(), seq_num, m_fetch_cycle, m_pseq->getLocalCycle());
//print source and dest regs
DEBUG_OUT(" SOURCES: ");
for(int i=0; i < SI_MAX_SOURCE; ++i){
reg_id_t & source = getSourceReg(i);
if(!source.isZero()){
DEBUG_OUT("( [%d] V: %d P: %d Arf: %s WriterSN: %lld WrittenCycle: %lld State: 0x%x)", i,source.getVanilla(), source.getPhysical(), source.rid_type_menomic( source.getRtype() ), source.getARF()->getWriterSeqnum( source, m_proc ), source.getARF()->getWrittenCycle( source, m_proc ), source.getVanillaState() );
}
}
DEBUG_OUT(" DESTS: ");
for(int i=0; i < SI_MAX_DEST; ++i){
reg_id_t & dest = getDestReg(i);
if(!dest.isZero()){
DEBUG_OUT("( [%d] V: %d P: %d Arf: %s )", i,dest.getVanilla(), dest.getPhysical(), dest.rid_type_menomic( dest.getRtype() ));
}
}
DEBUG_OUT("\n");
#endif
// execute the instruction using the jump table
pmf_dynamicExecute pmf = m_jump_table[si->getOpcode()];
(this->*pmf)();
// Due to functional bugs sometimes m_actual.pc will be -1
//ASSERT( m_actual.pc != (my_addr_t) -1 );
} else {
// NOT executed!
dp_control_t dp_value;
dp_value.m_at = &m_actual;
dp_value.m_taken = false;
dp_value.m_annul = si->getAnnul();
dp_value.m_offset = si->getOffset();
// do the operation
exec_fn_execute( (i_opcode) si->getOpcode(), (dp_int_t *) &dp_value );
// write result back to this dynamic instruction
m_isTaken = dp_value.m_taken;
}
SetStage(COMPLETE_STAGE);
#ifdef DEBUG_DYNAMIC
char buf[128];
s->printDisassemble(buf);
DEBUG_OUT("control_inst_t: AFTER Execute %s NAV[ %d ] seqnum[ %lld ] fetched[ %lld ] cycle[ %lld ] PredPC[ 0x%llx ] ActualPC[ 0x%llx ] PredNPC[ 0x%llx ] ActualNPC[ 0x%llx ] PredCWP[ 0x%x ] ActualCWP[ 0x%x ] PredTL[ 0x%x ] ActualTL[ 0x%x ] PredPstate[ 0x%x ] ActualPstate[ 0x%x ]\n", buf, getInstrNAV(), seq_num, m_fetch_cycle, m_pseq->getLocalCycle(), m_predicted.pc, m_actual.pc, m_predicted.npc, m_actual.npc, m_predicted.cwp, m_actual.cwp, m_predicted.tl, m_actual.tl, m_predicted.pstate, m_actual.pstate);
#endif
// All control op should be checked, all of them can mis-predict
// if the predicted PC, nPC pairs don't match with actual, cause exeception
if ( (m_predicted.pc != m_actual.pc ||
m_predicted.npc != m_actual.npc ||
m_predicted.cwp != m_actual.cwp ||
m_predicted.tl != m_actual.tl ||
m_predicted.pstate != m_actual.pstate) ) {
/* There was a branch mis-prediction --
* patch up branch predictor state */
#ifdef DEBUG_DYNAMIC
char buf[128];
s->printDisassemble(buf);
DEBUG_OUT("[ %d ] control_inst_t: MISPREDICT %s NAV[ %d ] seqnum[ %lld ] fetched[ %lld ] cycle[ %lld ] PredPC[ 0x%llx ] ActualPC[ 0x%llx ] PredNPC[ 0x%llx ] ActualNPC[ 0x%llx ] PredCWP[ 0x%x ] ActualCWP[ 0x%x ] PredTL[ 0x%x ] ActualTL[ 0x%x ] PredPstate[ 0x%x ] ActualPstate[ 0x%x ]\n", m_pseq->getID(), buf, getInstrNAV(), seq_num, m_fetch_cycle, m_pseq->getLocalCycle(), m_predicted.pc, m_actual.pc, m_predicted.npc, m_actual.npc, m_predicted.cwp, m_actual.cwp, m_predicted.tl, m_actual.tl, m_predicted.pstate, m_actual.pstate);
#endif
// This preformatted debugging information is left for your convenience
// NOT very useful here, bc this might indicate a misprediction AFTER another misprediction
// print this out inside Retire()!
/*
char buf[128];
s->printDisassemble( buf );
if (m_predicted.cwp != m_actual.cwp) {
m_pseq->out_info("CONTROLOP: CWP mispredict: predicted[ %d ] actual[ %d ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] %s\n",
m_predicted.cwp, m_actual.cwp, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, buf);
}
if (m_predicted.tl != m_actual.tl) {
m_pseq->out_info("CONTROLOP: TL mispredict: predicted[ %d ] actual[ %d ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] %s\n",
m_predicted.tl, m_actual.tl, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, buf);
}
if (m_predicted.pstate != m_actual.pstate) {
m_pseq->out_info("CONTROLOP: PSTATE mispredict: predicted[ 0x%0x ] actual[ 0x%0x ] type=%s seqnum[ %lld ] VPC[ 0x%llx ] PC[ 0x%llx ] fetched[ %lld ] executed[ %lld ] correctPC[ 0x%llx ] %s\n",
m_predicted.pstate, m_actual.pstate, pstate_t::branch_type_menomic[s->getBranchType()], seq_num, getVPC(), getPC(), m_fetch_cycle, m_event_times[EVENT_TIME_EXECUTE] + m_fetch_cycle, m_actual.pc, buf);
}
*/
markEvent(EVENT_BRANCH_MISPREDICT);
if (s->getBranchType() == BRANCH_COND ||
s->getBranchType() == BRANCH_PCOND ) {
// flip the last bit of the history to correct the misprediction
m_pred_state.cond_state = m_pred_state.cond_state ^ 1;
} else if (s->getBranchType() == BRANCH_INDIRECT ||
(s->getBranchType() == BRANCH_CALL && s->getOpcode() != i_call) ) {
/*
m_pseq->out_info(" INDIRECT: predicted 0x%0llx, 0x%0llx\n",
m_predicted.pc, m_predicted.npc);
m_pseq->out_info(" INDIRECT: actual 0x%0llx, 0x%0llx\n",
m_actual.pc, m_actual.npc);
*/
m_pseq->getIndirectBP()->FixupState(&(m_pred_state.indirect_state),
getVPC());
}
// no predictor fixup on PRIV, TRAP or TRAP_RETURN right now
// TASK: should update the BTB here
// TASK: determine the fetch location (and state)
m_actual.gset = pstate_t::getGlobalSet( m_actual.pstate );
/* cause a branch misprediction exception */
m_pseq->raiseException(EXCEPT_MISPREDICT, getWindowIndex(),
(enum i_opcode) s->getOpcode(),
&m_actual, 0, BRANCHPRED_MISPRED_PENALTY, m_proc );
}
}
