/* Erratum 350 */
static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
{
u8 u8Channel;
u8 u8Receiver;
u32 u32Addr;
u8 u8Valid;
u32 u32DctDev;
// 1. dummy read for each installed DIMM */
for (u8Channel = 0; u8Channel < 2; u8Channel++) {
// This will be 0 for vaild DIMMS, eles 8
u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel);
for (; u8Receiver < 8; u8Receiver += 2) {
u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
if(!u8Valid) { /* Address not supported on current CS */
print_t("vErrata350: Address not supported on current CS\n");
continue;
}
print_t("vErrata350: dummy read \n");
read32_fs(u32Addr);
}
}
print_t("vErrata350: step 2a\n");
/* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
u32DctDev = pDCTstat->dev_dct;
Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
/* ^--- value
^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
if(!pDCTstat->GangedMode) {
print_t("vErrata350: step 2b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
/* ^--- value
^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
}
print_t("vErrata350: step 3\n");
/* 3. Wait at least 300 nanoseconds. */
coreDelay(1);
print_t("vErrata350: step 4\n");
/* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
if(!pDCTstat->GangedMode) {
print_t("vErrata350: step 4b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
}
print_t("vErrata350: step 5\n");
/* 5. Wait at least 2 microseconds. */
coreDelay(2);
}
void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat)
{
/* Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations
* In TX FIFO
* Solution: BIOS should program DRAM Control Register[RdPtrInit] = 5h,
* (F2x[1, 0]78[3:0] = 5h).
* Silicon Status: Fixed In Rev B0
*/
/* Bug#15880: Determine validity of reset settings for DDR PHY timing
* regi..
* Solution: At least, set WrDqs fine delay to be 0 for DDR2 training.
*/
u32 dev;
u32 reg_off;
u32 index_reg;
u32 index;
u32 reg;
u32 val;
u32 tmp;
u32 Channel;
tmp = pDCTstat->LogicalCPUID;
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
dev = pDCTstat->dev_dct;
index = 0;
for(Channel = 0; Channel<2; Channel++) {
index_reg = 0x98 + 0x100 * Channel;
val = Get_NB32_index_wait(dev, index_reg, 0x0d004007);
val |= 0x3ff;
Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val);
}
for(Channel = 0; Channel<2; Channel++) {
if(pDCTstat->GangedMode && Channel)
break;
reg_off = 0x100 * Channel;
reg = 0x78 + reg_off;
val = Get_NB32(dev, reg);
val &= ~(0x07);
val |= 5;
Set_NB32(dev, reg, val);
}
for(Channel = 0; Channel<2; Channel++) {
reg_off = 0x100 * Channel;
val = 0;
index_reg = 0x98 + reg_off;
for( index = 0x30; index < (0x45 + 1); index++) {
Set_NB32_index_wait(dev, index_reg, index, val);
}
}
}
}
static inline void Set_NB32_index_wait_DCT(uint32_t dev, uint8_t dct, uint32_t index_reg, uint32_t index, uint32_t data)
{
if (is_fam15h()) {
/* Obtain address of function 0x1 */
uint32_t dev_map = (dev & (~(0x7 << 12))) | (0x1 << 12);
fam15h_switch_dct(dev_map, dct);
Set_NB32_index_wait(dev, index_reg, index, data);
} else {
Set_NB32_index_wait(dev, (0x100 * dct) + index_reg, index, data);
}
}
