u_int
decode_fpu(unsigned int Fpu_register[], unsigned int trap_counts[])
{
unsigned int current_ir, excp;
int target, exception_index = 1;
boolean inexact;
unsigned int aflags;
unsigned int bflags;
unsigned int excptype;
/* Keep stats on how many floating point exceptions (based on type)
* that happen. Want to keep this overhead low, but still provide
* some information to the customer. All exits from this routine
* need to restore Fpu_register[0]
*/
bflags=(Fpu_register[0] & 0xf8000000);
Fpu_register[0] &= 0x07ffffff;
/* exception_index is used to index the exception register queue. It
* always points at the last register that contains a valid exception. A
* zero value implies no exceptions (also the initialized value). Setting
* the T-bit resets the exception_index to zero.
*/
/*
* Check for reserved-op exception. A reserved-op exception does not
* set any exception registers nor does it set the T-bit. If the T-bit
* is not set then a reserved-op exception occurred.
*
* At some point, we may want to report reserved op exceptions as
* illegal instructions.
*/
if (!Is_tbit_set()) {
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
return SIGNALCODE(SIGILL, ILL_COPROC);
}
/*
* Is a coprocessor op.
*
* Now we need to determine what type of exception occurred.
*/
for (exception_index=1; exception_index<=MAX_EXCP_REG; exception_index++) {
current_ir = Excp_instr(exception_index);
/*
* On PA89: there are 5 different unimplemented exception
* codes: 0x1, 0x9, 0xb, 0x3, and 0x23. PA-RISC 2.0 adds
* another, 0x2b. Only these have the low order bit set.
*/
excptype = Excp_type(exception_index);
if (excptype & UNIMPLEMENTEDEXCEPTION) {
/*
* Clear T-bit and exception register so that
* we can tell if a trap really occurs while
* emulating the instruction.
*/
Clear_tbit();
Clear_excp_register(exception_index);
/*
* Now emulate this instruction. If a trap occurs,
* fpudispatch will return a non-zero number
*/
excp = fpudispatch(current_ir,excptype,0,Fpu_register);
/* accumulate the status flags, don't lose them as in hpux */
if (excp) {
/*
* We now need to make sure that the T-bit and the
* exception register contain the correct values
* before continuing.
*/
/*
* Set t-bit since it might still be needed for a
* subsequent real trap (I don't understand fully -PB)
*/
Set_tbit();
/* some of the following code uses
* Excp_type(exception_index) so fix that up */
Set_exceptiontype_and_instr_field(excp,current_ir,
Fpu_register[exception_index]);
if (excp == UNIMPLEMENTEDEXCEPTION) {
/*
* it is really unimplemented, so restore the
* TIMEX extended unimplemented exception code
*/
excp = excptype;
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
return SIGNALCODE(SIGILL, ILL_COPROC);
}
/* some of the following code uses excptype, so
* fix that up too */
excptype = excp;
}
/* handle exceptions other than the real UNIMPLIMENTED the
* same way as if the hardware had caused them */
if (excp == NOEXCEPTION)
/* For now use 'break', should technically be 'continue' */
break;
}
/*
* In PA89, the underflow exception has been extended to encode
* additional information. The exception looks like pp01x0,
* where x is 1 if inexact and pp represent the inexact bit (I)
* and the round away bit (RA)
*/
if (excptype & UNDERFLOWEXCEPTION) {
/* check for underflow trap enabled */
if (Is_underflowtrap_enabled()) {
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTUND);
} else {
/*
* Isn't a real trap; we need to
* return the default value.
*/
target = current_ir & fivebits;
#ifndef lint
if (Ibit(Fpu_register[exception_index])) inexact = TRUE;
else inexact = FALSE;
#endif
switch (Excp_format()) {
case SGL:
/*
* If ra (round-away) is set, will
* want to undo the rounding done
* by the hardware.
*/
if (Rabit(Fpu_register[exception_index]))
Sgl_decrement(Fpu_sgl(target));
/* now denormalize */
sgl_denormalize(&Fpu_sgl(target),&inexact,Rounding_mode());
break;
case DBL:
/*
* If ra (round-away) is set, will
* want to undo the rounding done
* by the hardware.
*/
if (Rabit(Fpu_register[exception_index]))
Dbl_decrement(Fpu_dblp1(target),Fpu_dblp2(target));
/* now denormalize */
dbl_denormalize(&Fpu_dblp1(target),&Fpu_dblp2(target),
&inexact,Rounding_mode());
break;
}
if (inexact) Set_underflowflag();
/*
* Underflow can generate an inexact
* exception. If inexact trap is enabled,
* want to do an inexact trap, otherwise
* set inexact flag.
*/
if (inexact && Is_inexacttrap_enabled()) {
/*
* Set exception field of exception register
* to inexact, parm field to zero.
* Underflow bit should be cleared.
*/
Set_exceptiontype(Fpu_register[exception_index],
INEXACTEXCEPTION);
Set_parmfield(Fpu_register[exception_index],0);
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTRES);
}
else {
/*
* Exception register needs to be cleared.
* Inexact flag needs to be set if inexact.
*/
Clear_excp_register(exception_index);
if (inexact) Set_inexactflag();
}
}
continue;
}
switch(Excp_type(exception_index)) {
case OVERFLOWEXCEPTION:
case OVERFLOWEXCEPTION | INEXACTEXCEPTION:
/* check for overflow trap enabled */
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
if (Is_overflowtrap_enabled()) {
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTOVF);
} else {
/*
* Isn't a real trap; we need to
* return the default value.
*/
target = current_ir & fivebits;
switch (Excp_format()) {
case SGL:
Sgl_setoverflow(Fpu_sgl(target));
break;
case DBL:
Dbl_setoverflow(Fpu_dblp1(target),Fpu_dblp2(target));
break;
}
Set_overflowflag();
/*
* Overflow always generates an inexact
* exception. If inexact trap is enabled,
* want to do an inexact trap, otherwise
* set inexact flag.
*/
if (Is_inexacttrap_enabled()) {
/*
* Set exception field of exception
* register to inexact. Overflow
* bit should be cleared.
*/
Set_exceptiontype(Fpu_register[exception_index],
INEXACTEXCEPTION);
update_trap_counts(Fpu_register, aflags, bflags,
trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTRES);
}
else {
/*
* Exception register needs to be cleared.
* Inexact flag needs to be set.
*/
Clear_excp_register(exception_index);
Set_inexactflag();
}
}
break;
case INVALIDEXCEPTION:
case OPC_2E_INVALIDEXCEPTION:
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTINV);
case DIVISIONBYZEROEXCEPTION:
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTDIV);
case INEXACTEXCEPTION:
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
return SIGNALCODE(SIGFPE, FPE_FLTRES);
default:
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
printk("%s(%d) Unknown FPU exception 0x%x\n", __FILE__,
__LINE__, Excp_type(exception_index));
return SIGNALCODE(SIGILL, ILL_COPROC);
case NOEXCEPTION: /* no exception */
/*
* Clear exception register in case
* other fields are non-zero.
*/
Clear_excp_register(exception_index);
break;
}
}
/*
* No real exceptions occurred.
*/
Clear_tbit();
update_trap_counts(Fpu_register, aflags, bflags, trap_counts);
return(NOTRAP);
}
int
sgl_fmpy(
sgl_floating_point *srcptr1,
sgl_floating_point *srcptr2,
sgl_floating_point *dstptr,
unsigned int *status)
{
register unsigned int opnd1, opnd2, opnd3, result;
register int dest_exponent, count;
register boolean inexact = FALSE, guardbit = FALSE, stickybit = FALSE;
boolean is_tiny;
opnd1 = *srcptr1;
opnd2 = *srcptr2;
/*
* set sign bit of result
*/
if (Sgl_sign(opnd1) ^ Sgl_sign(opnd2)) Sgl_setnegativezero(result);
else Sgl_setzero(result);
/*
* check first operand for NaN's or infinity
*/
if (Sgl_isinfinity_exponent(opnd1)) {
if (Sgl_iszero_mantissa(opnd1)) {
if (Sgl_isnotnan(opnd2)) {
if (Sgl_iszero_exponentmantissa(opnd2)) {
/*
* invalid since operands are infinity
* and zero
*/
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
Set_invalidflag();
Sgl_makequietnan(result);
*dstptr = result;
return(NOEXCEPTION);
}
/*
* return infinity
*/
Sgl_setinfinity_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
}
else {
/*
* is NaN; signaling or quiet?
*/
if (Sgl_isone_signaling(opnd1)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd1);
}
/*
* is second operand a signaling NaN?
*/
else if (Sgl_is_signalingnan(opnd2)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd2);
*dstptr = opnd2;
return(NOEXCEPTION);
}
/*
* return quiet NaN
*/
*dstptr = opnd1;
return(NOEXCEPTION);
}
}
/*
* check second operand for NaN's or infinity
*/
if (Sgl_isinfinity_exponent(opnd2)) {
if (Sgl_iszero_mantissa(opnd2)) {
if (Sgl_iszero_exponentmantissa(opnd1)) {
/* invalid since operands are zero & infinity */
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
Set_invalidflag();
Sgl_makequietnan(opnd2);
*dstptr = opnd2;
return(NOEXCEPTION);
}
/*
* return infinity
*/
Sgl_setinfinity_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/*
* is NaN; signaling or quiet?
*/
if (Sgl_isone_signaling(opnd2)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled()) return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd2);
}
/*
* return quiet NaN
*/
*dstptr = opnd2;
return(NOEXCEPTION);
}
/*
* Generate exponent
*/
dest_exponent = Sgl_exponent(opnd1) + Sgl_exponent(opnd2) - SGL_BIAS;
/*
* Generate mantissa
*/
if (Sgl_isnotzero_exponent(opnd1)) {
/* set hidden bit */
Sgl_clear_signexponent_set_hidden(opnd1);
}
else {
/* check for zero */
if (Sgl_iszero_mantissa(opnd1)) {
Sgl_setzero_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/* is denormalized, adjust exponent */
Sgl_clear_signexponent(opnd1);
Sgl_leftshiftby1(opnd1);
Sgl_normalize(opnd1,dest_exponent);
}
/* opnd2 needs to have hidden bit set with msb in hidden bit */
if (Sgl_isnotzero_exponent(opnd2)) {
Sgl_clear_signexponent_set_hidden(opnd2);
}
else {
/* check for zero */
if (Sgl_iszero_mantissa(opnd2)) {
Sgl_setzero_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/* is denormalized; want to normalize */
Sgl_clear_signexponent(opnd2);
Sgl_leftshiftby1(opnd2);
Sgl_normalize(opnd2,dest_exponent);
}
/* Multiply two source mantissas together */
Sgl_leftshiftby4(opnd2); /* make room for guard bits */
Sgl_setzero(opnd3);
/*
* Four bits at a time are inspected in each loop, and a
* simple shift and add multiply algorithm is used.
*/
for (count=1; count<SGL_P; count+=4) {
stickybit |= Slow4(opnd3);
Sgl_rightshiftby4(opnd3);
if (Sbit28(opnd1)) Sall(opnd3) += (Sall(opnd2) << 3);
if (Sbit29(opnd1)) Sall(opnd3) += (Sall(opnd2) << 2);
if (Sbit30(opnd1)) Sall(opnd3) += (Sall(opnd2) << 1);
if (Sbit31(opnd1)) Sall(opnd3) += Sall(opnd2);
Sgl_rightshiftby4(opnd1);
}
/* make sure result is left-justified */
if (Sgl_iszero_sign(opnd3)) {
Sgl_leftshiftby1(opnd3);
}
else {
/* result mantissa >= 2. */
dest_exponent++;
}
/* check for denormalized result */
while (Sgl_iszero_sign(opnd3)) {
Sgl_leftshiftby1(opnd3);
dest_exponent--;
}
/*
* check for guard, sticky and inexact bits
*/
stickybit |= Sgl_all(opnd3) << (SGL_BITLENGTH - SGL_EXP_LENGTH + 1);
guardbit = Sbit24(opnd3);
inexact = guardbit | stickybit;
/* re-align mantissa */
Sgl_rightshiftby8(opnd3);
/*
* round result
*/
if (inexact && (dest_exponent>0 || Is_underflowtrap_enabled())) {
Sgl_clear_signexponent(opnd3);
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result))
Sgl_increment(opnd3);
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result))
Sgl_increment(opnd3);
break;
case ROUNDNEAREST:
if (guardbit) {
if (stickybit || Sgl_isone_lowmantissa(opnd3))
Sgl_increment(opnd3);
}
}
if (Sgl_isone_hidden(opnd3)) dest_exponent++;
}
Sgl_set_mantissa(result,opnd3);
/*
* Test for overflow
*/
if (dest_exponent >= SGL_INFINITY_EXPONENT) {
/* trap if OVERFLOWTRAP enabled */
if (Is_overflowtrap_enabled()) {
/*
* Adjust bias of result
*/
Sgl_setwrapped_exponent(result,dest_exponent,ovfl);
*dstptr = result;
if (inexact)
if (Is_inexacttrap_enabled())
return(OVERFLOWEXCEPTION | INEXACTEXCEPTION);
else Set_inexactflag();
return(OVERFLOWEXCEPTION);
}
inexact = TRUE;
Set_overflowflag();
/* set result to infinity or largest number */
Sgl_setoverflow(result);
}
/*
* Test for underflow
*/
else if (dest_exponent <= 0) {
/* trap if UNDERFLOWTRAP enabled */
if (Is_underflowtrap_enabled()) {
/*
* Adjust bias of result
*/
Sgl_setwrapped_exponent(result,dest_exponent,unfl);
*dstptr = result;
if (inexact)
if (Is_inexacttrap_enabled())
return(UNDERFLOWEXCEPTION | INEXACTEXCEPTION);
else Set_inexactflag();
return(UNDERFLOWEXCEPTION);
}
/* Determine if should set underflow flag */
is_tiny = TRUE;
if (dest_exponent == 0 && inexact) {
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result)) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result)) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
case ROUNDNEAREST:
if (guardbit && (stickybit ||
Sgl_isone_lowmantissa(opnd3))) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
}
}
/*
* denormalize result or set to signed zero
*/
stickybit = inexact;
Sgl_denormalize(opnd3,dest_exponent,guardbit,stickybit,inexact);
/* return zero or smallest number */
if (inexact) {
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result)) {
Sgl_increment(opnd3);
}
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result)) {
Sgl_increment(opnd3);
}
break;
case ROUNDNEAREST:
if (guardbit && (stickybit ||
Sgl_isone_lowmantissa(opnd3))) {
Sgl_increment(opnd3);
}
break;
}
if (is_tiny) Set_underflowflag();
}
Sgl_set_exponentmantissa(result,opnd3);
}
else Sgl_set_exponent(result,dest_exponent);
*dstptr = result;
/* check for inexact */
if (inexact) {
if (Is_inexacttrap_enabled()) return(INEXACTEXCEPTION);
else Set_inexactflag();
}
return(NOEXCEPTION);
}
int
sgl_fdiv (sgl_floating_point * srcptr1, sgl_floating_point * srcptr2,
sgl_floating_point * dstptr, unsigned int *status)
{
register unsigned int opnd1, opnd2, opnd3, result;
register int dest_exponent, count;
register boolean inexact = FALSE, guardbit = FALSE, stickybit = FALSE;
boolean is_tiny;
opnd1 = *srcptr1;
opnd2 = *srcptr2;
/*
* set sign bit of result
*/
if (Sgl_sign(opnd1) ^ Sgl_sign(opnd2)) Sgl_setnegativezero(result);
else Sgl_setzero(result);
/*
* check first operand for NaN's or infinity
*/
if (Sgl_isinfinity_exponent(opnd1)) {
if (Sgl_iszero_mantissa(opnd1)) {
if (Sgl_isnotnan(opnd2)) {
if (Sgl_isinfinity(opnd2)) {
/*
* invalid since both operands
* are infinity
*/
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
Set_invalidflag();
Sgl_makequietnan(result);
*dstptr = result;
return(NOEXCEPTION);
}
/*
* return infinity
*/
Sgl_setinfinity_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
}
else {
/*
* is NaN; signaling or quiet?
*/
if (Sgl_isone_signaling(opnd1)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd1);
}
/*
* is second operand a signaling NaN?
*/
else if (Sgl_is_signalingnan(opnd2)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled())
return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd2);
*dstptr = opnd2;
return(NOEXCEPTION);
}
/*
* return quiet NaN
*/
*dstptr = opnd1;
return(NOEXCEPTION);
}
}
/*
* check second operand for NaN's or infinity
*/
if (Sgl_isinfinity_exponent(opnd2)) {
if (Sgl_iszero_mantissa(opnd2)) {
/*
* return zero
*/
Sgl_setzero_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/*
* is NaN; signaling or quiet?
*/
if (Sgl_isone_signaling(opnd2)) {
/* trap if INVALIDTRAP enabled */
if (Is_invalidtrap_enabled()) return(INVALIDEXCEPTION);
/* make NaN quiet */
Set_invalidflag();
Sgl_set_quiet(opnd2);
}
/*
* return quiet NaN
*/
*dstptr = opnd2;
return(NOEXCEPTION);
}
/*
* check for division by zero
*/
if (Sgl_iszero_exponentmantissa(opnd2)) {
if (Sgl_iszero_exponentmantissa(opnd1)) {
/* invalid since both operands are zero */
if (Is_invalidtrap_enabled()) return(INVALIDEXCEPTION);
Set_invalidflag();
Sgl_makequietnan(result);
*dstptr = result;
return(NOEXCEPTION);
}
if (Is_divisionbyzerotrap_enabled())
return(DIVISIONBYZEROEXCEPTION);
Set_divisionbyzeroflag();
Sgl_setinfinity_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/*
* Generate exponent
*/
dest_exponent = Sgl_exponent(opnd1) - Sgl_exponent(opnd2) + SGL_BIAS;
/*
* Generate mantissa
*/
if (Sgl_isnotzero_exponent(opnd1)) {
/* set hidden bit */
Sgl_clear_signexponent_set_hidden(opnd1);
}
else {
/* check for zero */
if (Sgl_iszero_mantissa(opnd1)) {
Sgl_setzero_exponentmantissa(result);
*dstptr = result;
return(NOEXCEPTION);
}
/* is denormalized; want to normalize */
Sgl_clear_signexponent(opnd1);
Sgl_leftshiftby1(opnd1);
Sgl_normalize(opnd1,dest_exponent);
}
/* opnd2 needs to have hidden bit set with msb in hidden bit */
if (Sgl_isnotzero_exponent(opnd2)) {
Sgl_clear_signexponent_set_hidden(opnd2);
}
else {
/* is denormalized; want to normalize */
Sgl_clear_signexponent(opnd2);
Sgl_leftshiftby1(opnd2);
while(Sgl_iszero_hiddenhigh7mantissa(opnd2)) {
Sgl_leftshiftby8(opnd2);
dest_exponent += 8;
}
if(Sgl_iszero_hiddenhigh3mantissa(opnd2)) {
Sgl_leftshiftby4(opnd2);
dest_exponent += 4;
}
while(Sgl_iszero_hidden(opnd2)) {
Sgl_leftshiftby1(opnd2);
dest_exponent += 1;
}
}
/* Divide the source mantissas */
/*
* A non_restoring divide algorithm is used.
*/
Sgl_subtract(opnd1,opnd2,opnd1);
Sgl_setzero(opnd3);
for (count=1;count<=SGL_P && Sgl_all(opnd1);count++) {
Sgl_leftshiftby1(opnd1);
Sgl_leftshiftby1(opnd3);
if (Sgl_iszero_sign(opnd1)) {
Sgl_setone_lowmantissa(opnd3);
Sgl_subtract(opnd1,opnd2,opnd1);
}
else Sgl_addition(opnd1,opnd2,opnd1);
}
if (count <= SGL_P) {
Sgl_leftshiftby1(opnd3);
Sgl_setone_lowmantissa(opnd3);
Sgl_leftshift(opnd3,SGL_P-count);
if (Sgl_iszero_hidden(opnd3)) {
Sgl_leftshiftby1(opnd3);
dest_exponent--;
}
}
else {
if (Sgl_iszero_hidden(opnd3)) {
/* need to get one more bit of result */
Sgl_leftshiftby1(opnd1);
Sgl_leftshiftby1(opnd3);
if (Sgl_iszero_sign(opnd1)) {
Sgl_setone_lowmantissa(opnd3);
Sgl_subtract(opnd1,opnd2,opnd1);
}
else Sgl_addition(opnd1,opnd2,opnd1);
dest_exponent--;
}
if (Sgl_iszero_sign(opnd1)) guardbit = TRUE;
stickybit = Sgl_all(opnd1);
}
inexact = guardbit | stickybit;
/*
* round result
*/
if (inexact && (dest_exponent > 0 || Is_underflowtrap_enabled())) {
Sgl_clear_signexponent(opnd3);
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result))
Sgl_increment_mantissa(opnd3);
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result))
Sgl_increment_mantissa(opnd3);
break;
case ROUNDNEAREST:
if (guardbit) {
if (stickybit || Sgl_isone_lowmantissa(opnd3))
Sgl_increment_mantissa(opnd3);
}
}
if (Sgl_isone_hidden(opnd3)) dest_exponent++;
}
Sgl_set_mantissa(result,opnd3);
/*
* Test for overflow
*/
if (dest_exponent >= SGL_INFINITY_EXPONENT) {
/* trap if OVERFLOWTRAP enabled */
if (Is_overflowtrap_enabled()) {
/*
* Adjust bias of result
*/
Sgl_setwrapped_exponent(result,dest_exponent,ovfl);
*dstptr = result;
if (inexact)
if (Is_inexacttrap_enabled())
return(OVERFLOWEXCEPTION | INEXACTEXCEPTION);
else Set_inexactflag();
return(OVERFLOWEXCEPTION);
}
Set_overflowflag();
/* set result to infinity or largest number */
Sgl_setoverflow(result);
inexact = TRUE;
}
/*
* Test for underflow
*/
else if (dest_exponent <= 0) {
/* trap if UNDERFLOWTRAP enabled */
if (Is_underflowtrap_enabled()) {
/*
* Adjust bias of result
*/
Sgl_setwrapped_exponent(result,dest_exponent,unfl);
*dstptr = result;
if (inexact)
if (Is_inexacttrap_enabled())
return(UNDERFLOWEXCEPTION | INEXACTEXCEPTION);
else Set_inexactflag();
return(UNDERFLOWEXCEPTION);
}
/* Determine if should set underflow flag */
is_tiny = TRUE;
if (dest_exponent == 0 && inexact) {
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result)) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result)) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
case ROUNDNEAREST:
if (guardbit && (stickybit ||
Sgl_isone_lowmantissa(opnd3))) {
Sgl_increment(opnd3);
if (Sgl_isone_hiddenoverflow(opnd3))
is_tiny = FALSE;
Sgl_decrement(opnd3);
}
break;
}
}
/*
* denormalize result or set to signed zero
*/
stickybit = inexact;
Sgl_denormalize(opnd3,dest_exponent,guardbit,stickybit,inexact);
/* return rounded number */
if (inexact) {
switch (Rounding_mode()) {
case ROUNDPLUS:
if (Sgl_iszero_sign(result)) {
Sgl_increment(opnd3);
}
break;
case ROUNDMINUS:
if (Sgl_isone_sign(result)) {
Sgl_increment(opnd3);
}
break;
case ROUNDNEAREST:
if (guardbit && (stickybit ||
Sgl_isone_lowmantissa(opnd3))) {
Sgl_increment(opnd3);
}
break;
}
if (is_tiny) Set_underflowflag();
}
Sgl_set_exponentmantissa(result,opnd3);
}
else Sgl_set_exponent(result,dest_exponent);
*dstptr = result;
/* check for inexact */
if (inexact) {
if (Is_inexacttrap_enabled()) return(INEXACTEXCEPTION);
else Set_inexactflag();
}
return(NOEXCEPTION);
}
