static inline void spi_transmit_single_package(spi_package* package){
spi_current_package = package;
/*copy data into fifo*/
for(int i=0; i<(*spi_current_package).length; i++){
SSPDR = (*spi_current_package).data[i];
}
/*set bit mode (8bit or 16bit)*/
SSPCR0 = (*spi_current_package).bit_mode | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR;
/*select the device*/
(*spi_current_package).slave_select();
/* enable SPI and send package data*/
SpiClearRti();
SpiEnableRti();
SpiEnable();
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if ( bit_is_set(SSPMIS, RTMIS)) { /* Rx timeout */
SpiReceive();
SpiClearRti(); /* clear interrupt */
SpiDisableRti();
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx fifo is half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if (bit_is_set(SSPMIS, RTMIS)) { /* Rx fifo is not empty and no receive took place in the last 32 bits period */
SpiUnselectCurrentSlave();
SpiReceive();
SpiDisableRti();
SpiClearRti(); /* clear interrupt */
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
static void SSP_ISR(void) {
ISR_ENTRY();
//start the device interrupt handler
(*spi_current_package).spi_interrupt_handler();
//unselect device, disable spi
(*spi_current_package).slave_unselect();
SpiClearRti();
SpiDisableRti();
SpiDisable();
// check if more data to send
if (spi_package_buffer_insert_idx != spi_package_buffer_extract_idx) {
spi_transmit_single_package(&spi_package_buffer[spi_package_buffer_extract_idx]);
spi_package_buffer_extract_idx++;
spi_package_buffer_extract_idx %= SPI_PACKAGE_BUFFER_SIZE;
} else {
spi_transmit_running = 0; // clear running flag
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void)
{
ISR_ENTRY();
if (baro_scp_status == STA_INITIALISING) {
uint8_t foo1 = SSPDR;
uint8_t foo2 = SSPDR;
baro_scp_status = STA_IDLE;
foo1 = foo2;
} else if (baro_scp_status == STA_IDLE) {
uint8_t foo0 = SSPDR;
baro_scp_temperature = SSPDR << 8;
baro_scp_temperature += SSPDR;
if (baro_scp_temperature & 0x2000) {
baro_scp_temperature |= 0xC000;
}
baro_scp_temperature *= 5;
uint8_t foo1 = SSPDR;
uint32_t datard8 = SSPDR << 16;
uint8_t foo2 = SSPDR;
baro_scp_pressure = SSPDR << 8;
baro_scp_pressure += SSPDR;
baro_scp_pressure += datard8;
baro_scp_pressure *= 25;
baro_scp_available = TRUE;
foo1 = foo2;
foo0 = foo2;
}
ScpUnselect();
SpiClearRti();
SpiDisable();
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void) {
ISR_ENTRY();
while (bit_is_set(SSPSR, RNE)) {
uint16_t data = SSPDR;
if (bit_is_set(data, MAX3100_R_BIT)) { /* Data available */
max3100_rx_buf[max3100_rx_insert_idx] = data & 0xff;
max3100_rx_insert_idx++; // automatic overflow because len=256
read_bytes = true;
}
if (bit_is_set(data, MAX3100_T_BIT) && (max3100_status == MAX3100_STATUS_READING)) { /* transmit buffer empty */
max3100_transmit_buffer_empty = true;
}
}
SpiClearRti(); /* clear interrupt */
SpiDisableRti();
SpiDisable ();
Max3100Unselect();
max3100_status = MAX3100_STATUS_IDLE;
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
