void spi_transmit(spi_package* package) {
int temp;
unsigned cpsr;
temp = (spi_package_buffer_insert_idx + 1) % SPI_PACKAGE_BUFFER_SIZE; // calculate the next queue position
if (temp == spi_package_buffer_extract_idx) { // check if there is free space in the send queue
return; // no room
}
cpsr = disableIRQ(); // disable global interrupts
SpiDisableRti(); // disable RTI interrupts
restoreIRQ(cpsr); // restore global interrupts
spi_package_buffer[spi_package_buffer_insert_idx] = *package; // add data to queue
spi_package_buffer_insert_idx = temp; // increase insert pointer
if (spi_transmit_running==0) // check if in process of sending data
{
spi_transmit_running = 1; // set running flag
spi_transmit_single_package(&spi_package_buffer[spi_package_buffer_extract_idx]);
spi_package_buffer_extract_idx++;
spi_package_buffer_extract_idx %= SPI_PACKAGE_BUFFER_SIZE;
}
cpsr = disableIRQ(); // disable global interrupts
SpiEnableRti(); // enable RTI interrupts
restoreIRQ(cpsr); // restore global interrupts
}
/* write 0x0A to 0x03 */
static void baro_scp_start_high_res_measurement(void)
{
uint8_t cmd = 0x03 << 2 | 0x02;
uint8_t data = 0x0A;
ScpSelect();
SSPDR = cmd;
SSPDR = data;
SpiEnableRti();
SpiEnable();
}
void EXTINT2_ISR(void) {
ISR_ENTRY();
/* read dummy control byte reply */
uint8_t foo __attribute__ ((unused)) = SSPDR;
/* trigger 2 bytes read */
SSPDR = 0;
SSPDR = 0;
/* enable timeout interrupt */
SpiEnableRti();
/* clear EINT2 */
SetBit(EXTINT,MM_DRDY_EINT); /* clear EINT2 */
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
static inline void spi_transmit_single_package(spi_package* package){
spi_current_package = package;
/*copy data into fifo*/
for(int i=0; i<(*spi_current_package).length; i++){
SSPDR = (*spi_current_package).data[i];
}
/*set bit mode (8bit or 16bit)*/
SSPCR0 = (*spi_current_package).bit_mode | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR;
/*select the device*/
(*spi_current_package).slave_select();
/* enable SPI and send package data*/
SpiClearRti();
SpiEnableRti();
SpiEnable();
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if ( bit_is_set(SSPMIS, RTMIS)) { /* Rx timeout */
SpiReceive();
SpiClearRti(); /* clear interrupt */
SpiDisableRti();
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
void SPI1_ISR(void) {
ISR_ENTRY();
if (bit_is_set(SSPMIS, TXMIS)) { /* Tx fifo is half empty */
SpiTransmit();
SpiReceive();
SpiEnableRti();
}
if (bit_is_set(SSPMIS, RTMIS)) { /* Rx fifo is not empty and no receive took place in the last 32 bits period */
SpiUnselectCurrentSlave();
SpiReceive();
SpiDisableRti();
SpiClearRti(); /* clear interrupt */
SpiDisable();
spi_message_received = TRUE;
}
VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
ISR_EXIT();
}
