static DECLFW(Mapper69_write)
{
switch(A&0xE000)
{
case 0x8000:reg_select=V;break;
case 0xa000:
reg_select&=0xF;
if(reg_select < 8)
{
CHRRegs[reg_select] = V;
SyncCHR();
}
else
switch(reg_select&0x0f)
{
case 0x8: wram_control = V; SyncPRG(); break;
case 0x9: PRGRegs[0] = V & 0x3F; SyncPRG(); break;
case 0xa: PRGRegs[1] = V & 0x3F; SyncPRG(); break;
case 0xb: PRGRegs[2] = V & 0x3F; SyncPRG(); break;
case 0xc: Mirroring = V & 0x3; SyncMirroring(); break;
case 0xd:IRQa=V; X6502_IRQEnd(MDFN_IQEXT); break;
case 0xe:IRQCount&=0xFF00;IRQCount|=V;break;
case 0xf:IRQCount&=0x00FF;IRQCount|=V<<8;break;
}
break;
}
}
static int StateAction(StateMem *sm, int load, int data_only)
{
SFORMAT StateRegs[] =
{
SFVARN(reg_select, "FM7S"),
SFVARN(wram_control, "FM7W"),
SFARRAYN(sr, 0x10, "FM7SR"),
SFVARN(sr_index, "FM7I"),
SFARRAY(PRGRegs, 3),
SFARRAY(CHRRegs, 8),
SFVAR(Mirroring),
SFARRAY32(vcount, 3),
SFARRAY32(dcount, 3),
SFVAR(IRQa),
SFVAR(IRQCount),
SFARRAY(WRAM, 8192),
SFEND
};
int ret = MDFNSS_StateAction(sm, load, data_only, StateRegs, "MAPR");
if(load)
{
SyncCHR();
SyncPRG();
SyncMirroring();
}
return(ret);
}
static void Reset(CartInfo *info)
{
sr_index = 0;
wram_control = 0;
memset(sr, 0xFF, sizeof(sr)); // Setting all bits will cause sound output to be disabled on reset.
PRGRegs[0] = PRGRegs[1] = PRGRegs[2] = 0x3F;
Mirroring = info->mirror ? 0 : 1; // Do any mapper 69 boards use hardware-fixed mirroring?
SyncPRG();
SyncMirroring();
setprg8(0xe000, 0x3F);
}
