static void __bctimer_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { unsigned int saved; switch (mode) { case CLOCK_EVT_MODE_PERIODIC: __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, PERIOD_MODE); __raw_writel(LATCH, TIMER_LOAD(BC_CPU, BC_TIMER)); __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, PERIOD_MODE); __raw_writel(TIMER_INT_EN, TIMER_INT(BC_CPU, BC_TIMER)); break; case CLOCK_EVT_MODE_ONESHOT: __raw_writel(LATCH, TIMER_LOAD(BC_CPU, BC_TIMER)); __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE); __raw_writel(TIMER_INT_EN, TIMER_INT(BC_CPU, BC_TIMER)); break; case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: __raw_writel(TIMER_INT_CLR, TIMER_INT(BC_CPU, BC_TIMER)); saved = __raw_readl(TIMER_CTL(BC_CPU, BC_TIMER)) & PERIOD_MODE; __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, saved); break; case CLOCK_EVT_MODE_RESUME: saved = __raw_readl(TIMER_CTL(BC_CPU, BC_TIMER)) & PERIOD_MODE; __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, saved); break; } }
void sec_debug_print_gptimer_reg(void) { printk("%s: gptimer-clockevent\n",__func__); printk("load reg: 0x%x\n",__raw_readl(TIMER_LOAD(0,0))); printk("value reg: 0x%x\n",__raw_readl(TIMER_VALUE(0,0))); printk("control reg: 0x%x\n",__raw_readl(TIMER_CTL(0,0))); printk("interrupt reg: 0x%x\n",__raw_readl(TIMER_INT(0,0))); printk("%s: gptimer-clocksource\n",__func__); printk("load reg: 0x%x\n",__raw_readl(TIMER_LOAD(0,2))); printk("value reg: 0x%x\n",__raw_readl(TIMER_VALUE(0,2))); printk("control reg: 0x%x\n",__raw_readl(TIMER_CTL(0,2))); printk("interrupt reg: 0x%x\n",__raw_readl(TIMER_INT(0,2))); }
void __init gemini_timer_init(void) { unsigned int tick_rate, reg_v; reg_v = __raw_readl(IO_ADDRESS(GEMINI_GLOBAL_BASE + GLOBAL_STATUS)); tick_rate = REG_TO_AHB_SPEED(reg_v) * 1000000; printk(KERN_INFO "Bus: %dMHz", tick_rate / 1000000); tick_rate /= 6; /* APB bus run AHB*(1/6) */ switch(reg_v & CPU_AHB_RATIO_MASK) { case CPU_AHB_1_1: printk(KERN_CONT "(1/1)\n"); break; case CPU_AHB_3_2: printk(KERN_CONT "(3/2)\n"); break; case CPU_AHB_24_13: printk(KERN_CONT "(24/13)\n"); break; case CPU_AHB_2_1: printk(KERN_CONT "(2/1)\n"); break; } /* * Make irqs happen for the system timer */ setup_irq(IRQ_TIMER2, &gemini_timer_irq); /* Start the timer */ __raw_writel(tick_rate / HZ, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE))); __raw_writel(tick_rate / HZ, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE))); __raw_writel(TIMER_2_CR_ENABLE | TIMER_2_CR_INT, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE))); }
static int __gptimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { __gptimer_ctl(EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(EVENT_TIMER)); __gptimer_ctl(EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
static int __bctimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(BC_CPU, BC_TIMER))) ; __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(BC_CPU, BC_TIMER)); __gptimer_ctl(BC_CPU, BC_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
static int __gptimer_set_next_event(unsigned long cycles, struct clock_event_device *c) { int cpu = smp_processor_id(); while (TIMER_INT_BUSY & __raw_readl(TIMER_INT(cpu, EVENT_TIMER))) ; __gptimer_ctl(cpu, EVENT_TIMER, TIMER_DISABLE, ONETIME_MODE); __raw_writel(cycles, TIMER_LOAD(cpu, EVENT_TIMER)); __gptimer_ctl(cpu, EVENT_TIMER, TIMER_ENABLE, ONETIME_MODE); return 0; }
/* ****************************************************************** */ static void __gptimer_clocksource_init(const char *name, unsigned long hz) { /* disalbe irq since it's just a read source */ __raw_writel(0, TIMER_INT(SOURCE_TIMER)); __gptimer_ctl(SOURCE_TIMER, TIMER_DISABLE, PERIOD_MODE); __raw_writel(ULONG_MAX, TIMER_LOAD(SOURCE_TIMER)); __gptimer_ctl(SOURCE_TIMER, TIMER_ENABLE, PERIOD_MODE); clocksource_mmio_init(TIMER_VALUE(SOURCE_TIMER), name, hz, 300, 32, clocksource_mmio_readl_down); }
static void __gptimer_clocksource_init(void) { /* disalbe irq since it's just a read source */ __raw_writel(0, TIMER_INT(e_cpu, SOURCE_TIMER)); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_DISABLE | TIMER_NEW, PERIOD_MODE); __raw_writel(ULONG_MAX, TIMER_LOAD(e_cpu, SOURCE_TIMER)); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_NEW, PERIOD_MODE); __gptimer_ctl(e_cpu, SOURCE_TIMER, TIMER_ENABLE | TIMER_NEW, PERIOD_MODE); if (clocksource_register_hz (&clocksource_sprd, gptimer_clock_source_freq)) printk("%s: can't register clocksource\n", clocksource_sprd.name); }