void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
mvme5100_set_bat();
isa_io_base = MVME5100_ISA_IO_BASE;
isa_mem_base = MVME5100_ISA_MEM_BASE;
pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
ppc_md.setup_arch = mvme5100_setup_arch;
ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
ppc_md.init_IRQ = mvme5100_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.init = mvme5100_init2;
ppc_md.restart = mvme5100_restart;
ppc_md.power_off = mvme5100_power_off;
ppc_md.halt = mvme5100_halt;
ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
ppc_md.setup_io_mappings = mvme5100_map_io;
TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1,
MVME5100_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
}
static void __init
ocotea_setup_arch(void)
{
unsigned char *addr;
unsigned long long mac64;
bd_t *bip = (bd_t *) __res;
/* Retrieve MAC addresses from flash */
addr = ioremap64(OCOTEA_MAC_BASE, OCOTEA_MAC_SIZE);
mac64 = simple_strtoull(addr, 0, 16);
memcpy(bip->bi_enetaddr[0], (char *)&mac64+2, 6);
mac64 = simple_strtoull(addr+OCOTEA_MAC1_OFFSET, 0, 16);
memcpy(bip->bi_enetaddr[1], (char *)&mac64+2, 6);
iounmap(addr);
/* Set EMAC PHY map to not probe address 0x00 */
emac_phy_map[0] = 0x00000001;
emac_phy_map[1] = 0x00000001;
#if !defined(CONFIG_BDI_SWITCH)
/*
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
*/
mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
#endif
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = to_kdev_t(0x0100); /* /dev/ram */
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = to_kdev_t(0x00ff); /* /dev/nfs */
#else
ROOT_DEV = to_kdev_t(0x0301); /* /dev/hda1 */
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
static void __init taiga_setup_arch(void)
{
loops_per_jiffy = 50000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
if (ppc_md.progress)
ppc_md.progress("taiga_setup_arch: setup_bridge", 0);
/* setup PCI host bridge */
taiga_setup_bridge();
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
printk(KERN_INFO "Taiga Platform\n");
printk(KERN_INFO
"Jointly ported by Freescale and Tundra Semiconductor\n");
printk(KERN_INFO
"Enabling L2 cache then enabling the HID0 prefetch engine.\n");
_set_L2CR(L2CR_L2E);
taiga_l2cr_prefetch_enable();
TODC_INIT(TODC_TYPE_MK48T35, 0, 0, TAIGA_NVRAM_BASE_ADDR, 8);
}
void __init
cpci405_setup_arch(void)
{
ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 0);
TODC_INIT(TODC_TYPE_MK48T35, cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
}
static void __init
ebony_setup_arch(void)
{
struct ocp_def *def;
struct ocp_func_emac_data *emacdata;
/* Set mac_addr for each EMAC */
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
emacdata = def->additions;
emacdata->phy_map = 0x00000001; /* Skip 0x00 */
emacdata->phy_mode = PHY_MODE_RMII;
memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
emacdata = def->additions;
emacdata->phy_map = 0x00000001; /* Skip 0x00 */
emacdata->phy_mode = PHY_MODE_RMII;
memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ebony_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ebony_early_serial_map();
/* Identify the system */
printk("IBM Ebony port (MontaVista Software, Inc. ([email protected]))\n");
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Map in board regs, etc. */
pplus_set_bat();
isa_io_base = PREP_ISA_IO_BASE;
isa_mem_base = PREP_ISA_MEM_BASE;
pci_dram_offset = PREP_PCI_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_do_canonicalize_irqs = 1;
ppc_md.setup_arch = pplus_setup_arch;
ppc_md.show_cpuinfo = pplus_show_cpuinfo;
ppc_md.init_IRQ = pplus_init_IRQ;
/* this gets changed later on if we have an OpenPIC -- Cort */
ppc_md.get_irq = i8259_irq;
ppc_md.init = pplus_init2;
ppc_md.restart = pplus_restart;
ppc_md.power_off = pplus_power_off;
ppc_md.halt = pplus_halt;
TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
PREP_NVRAM_DATA, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
ppc_md.find_end_of_memory = pplus_find_end_of_memory;
ppc_md.setup_io_mappings = pplus_map_io;
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = pplus_ide_default_irq;
ppc_ide_md.default_io_base = pplus_ide_default_io_base;
ppc_ide_md.ide_init_hwif = pplus_ide_init_hwif_ports;
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
#ifdef CONFIG_SMP
smp_ops = &pplus_smp_ops;
#endif /* CONFIG_SMP */
}
void __init
ev64360_setup_peripherals(void)
{
u32 base;
/* Set up window for boot CS */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* We only use the 32-bit flash */
mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
&ev64360_flash_size_0);
ev64360_flash_size_1 = 0;
mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
TODC_INIT(TODC_TYPE_DS1501, 0, 0,
ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
/* Set up Enet->SRAM window */
mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
/* Give enet r/w access to memory region */
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
#if defined(CONFIG_NOT_COHERENT_CACHE)
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
#else
mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
#endif
/*
* Setting the SRAM to 0. Note that this generates parity errors on
* internal data path in SRAM since it's first time accessing it
* while after reset it's not configured.
*/
memset(sram_base, 0, MV64360_SRAM_SIZE);
/* set up PCI interrupt controller */
ev64360_intr_setup();
}
void __init
walnut_setup_arch(void)
{
void *fpga_brdc;
unsigned char fpga_brdc_data;
void *fpga_enable;
void *fpga_polarity;
void *fpga_status;
void *fpga_trigger;
ppc4xx_setup_arch();
kb_data = ioremap(WALNUT_PS2_BASE, 8);
if (!kb_data) {
printk(KERN_CRIT
"walnut_setup_arch() kb_data ioremap failed\n");
return;
}
kb_cs = kb_data + 1;
fpga_status = ioremap(WALNUT_FPGA_BASE, 8);
if (!fpga_status) {
printk(KERN_CRIT
"walnut_setup_arch() fpga_status ioremap failed\n");
return;
}
fpga_enable = fpga_status + 1;
fpga_polarity = fpga_status + 2;
fpga_trigger = fpga_status + 3;
fpga_brdc = fpga_status + 4;
/* split the keyboard and mouse interrupts */
fpga_brdc_data = readb(fpga_brdc);
fpga_brdc_data |= 0x80;
writeb(fpga_brdc_data, fpga_brdc);
writeb(0x3, fpga_enable);
writeb(0x3, fpga_polarity);
writeb(0x3, fpga_trigger);
/* RTC step for the walnut */
walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
walnut_rtc_base, 8);
/* Identify the system */
printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. ([email protected])\n");
}
void __init
bubinga_setup_arch(void)
{
ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 1);
bubinga_early_serial_map();
/* RTC step for the evb405ep */
bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
bubinga_rtc_base, 8);
/* Identify the system */
printk("IBM Bubinga port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* Cover I/O space with a BAT */
/* yuck, better hope your ram size is a power of 2 -- paulus */
pcore_set_bat();
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ppc_md.setup_arch = pcore_setup_arch;
ppc_md.show_cpuinfo = pcore_show_cpuinfo;
ppc_md.init_IRQ = pcore_init_IRQ;
ppc_md.get_irq = i8259_irq;
ppc_md.find_end_of_memory = pcore_find_end_of_memory;
ppc_md.setup_io_mappings = pcore_map_io;
ppc_md.restart = pcore_restart;
ppc_md.power_off = pcore_power_off;
ppc_md.halt = pcore_halt;
TODC_INIT(TODC_TYPE_MK48T59,
PCORE_NVRAM_AS0,
PCORE_NVRAM_AS1,
PCORE_NVRAM_DATA,
8);
ppc_md.time_init = todc_time_init;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
}
static void __init
mcpn765_setup_arch(void)
{
struct pci_controller *hose;
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: enter", 0);
loops_per_jiffy = 50000000 / HZ;
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_SDA2;
#endif
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: find_bridges", 0);
/* Lookup PCI host bridges */
mcpn765_find_bridges();
hose = pci_bus_to_hose(0);
isa_io_base = (ulong)hose->io_base_virt;
TODC_INIT(TODC_TYPE_MK48T37,
(MCPN765_PHYS_NVRAM_AS0 - isa_io_base),
(MCPN765_PHYS_NVRAM_AS1 - isa_io_base),
(MCPN765_PHYS_NVRAM_DATA - isa_io_base),
8);
OpenPIC_InitSenses = mcpn765_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
printk("MCPN765 port (MontaVista Software, Inc. ([email protected]))\n");
if ( ppc_md.progress )
ppc_md.progress("mcpn765_setup_arch: exit", 0);
return;
}
static void __init
ocotea_setup_arch(void)
{
ocotea_set_emacdata();
ibm440gx_tah_enable();
/*
* Determine various clocks.
* To be completely correct we should get SysClk
* from FPGA, because it can be changed by on-board switches
* --ebs
*/
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
void __init
ash_setup_arch(void)
{
ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 3);
#ifdef CONFIG_DEBUG_BRINGUP
int i;
printk("\n");
printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
printk("\n");
printk("bi_s_version\t %s\n", bip->bi_s_version);
printk("bi_r_version\t %s\n", bip->bi_r_version);
printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
bip->bi_memsize / (1024 * 1000));
for (i = 0; i < EMAC_NUMS; i++) {
printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", i,
bip->bi_enetaddr[i][0], bip->bi_enetaddr[i][1],
bip->bi_enetaddr[i][2], bip->bi_enetaddr[i][3],
bip->bi_enetaddr[i][4], bip->bi_enetaddr[i][5]);
}
printk("bi_pci_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
bip->bi_pci_enetaddr[0], bip->bi_pci_enetaddr[1],
bip->bi_pci_enetaddr[2], bip->bi_pci_enetaddr[3],
bip->bi_pci_enetaddr[4], bip->bi_pci_enetaddr[5]);
printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
bip->bi_intfreq, bip->bi_intfreq / 1000000);
printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
bip->bi_busfreq, bip->bi_busfreq / 1000000);
printk("bi_pci_busfreq\t 0x%8.8x\t pci bus clock:\t %dMHz\n",
bip->bi_pci_busfreq, bip->bi_pci_busfreq / 1000000);
printk("\n");
#endif
/* RTC step for ash */
ash_rtc_base = (void *) ASH_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, ash_rtc_base, ash_rtc_base, ash_rtc_base,
8);
}
static void sbc82xx_time_init(void)
{
volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
/* Set up CS11 for RTC chip */
mc->memc_br11=0;
mc->memc_or11=0xffff0836;
mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
todc_info->nvram_data =
(unsigned int)ioremap(todc_info->nvram_data, 0x2000);
BUG_ON(!todc_info->nvram_data);
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.nvram_read_val = todc_direct_read_val;
ppc_md.nvram_write_val = todc_direct_write_val;
todc_time_init();
}
static void __init
lopec_setup_arch(void)
{
TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
ioremap(0xffe80000, 0x8000), 8);
loops_per_jiffy = 100000000/HZ;
lopec_find_bridges();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#elif defined(CONFIG_ROOT_NFS)
ROOT_DEV = Root_NFS;
#elif defined(CONFIG_BLK_DEV_IDEDISK)
ROOT_DEV = Root_HDA1;
#else
ROOT_DEV = Root_SDA1;
#endif
#ifdef CONFIG_PPCBUG_NVRAM
/* Read in NVRAM data */
init_prep_nvram();
/* if no bootargs, look in NVRAM */
if ( cmd_line[0] == '\0' ) {
char *bootargs;
bootargs = prep_nvram_get_var("bootargs");
if (bootargs != NULL) {
strcpy(cmd_line, bootargs);
/* again.. */
strcpy(saved_command_line, cmd_line);
}
}
#endif
}
static void __init
bamboo_setup_arch(void)
{
bamboo_set_emacdata();
ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
bamboo_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
bamboo_early_serial_map();
/* Identify the system */
printk("IBM Bamboo port (MontaVista Software, Inc. ([email protected]))\n");
}
static void __init
ocotea_setup_arch(void)
{
ocotea_set_emacdata();
ibm440gx_tah_enable();
/* Setup TODC access */
TODC_INIT(TODC_TYPE_DS1743,
0,
0,
ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
8);
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
ocotea_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
ocotea_early_serial_map();
/* Identify the system */
printk("IBM Ocotea port (MontaVista Software, Inc. <*****@*****.**>)\n");
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ppc_md.setup_arch = pcore_setup_arch;
ppc_md.show_cpuinfo = pcore_show_cpuinfo;
ppc_md.init_IRQ = pcore_init_IRQ;
ppc_md.get_irq = i8259_irq;
ppc_md.find_end_of_memory = pcore_find_end_of_memory;
ppc_md.setup_io_mappings = pcore_map_io;
ppc_md.restart = pcore_restart;
ppc_md.power_off = pcore_power_off;
ppc_md.halt = pcore_halt;
TODC_INIT(TODC_TYPE_MK48T59,
PCORE_NVRAM_AS0,
PCORE_NVRAM_AS1,
PCORE_NVRAM_DATA,
8);
ppc_md.time_init = todc_time_init;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_m48txx_read_val;
ppc_md.nvram_write_val = todc_m48txx_write_val;
}
void __init
sycamore_setup_arch(void)
{
#define SYCAMORE_PS2_BASE 0xF0100000
#define SYCAMORE_FPGA_BASE 0xF0300000
void *fpga_brdc;
unsigned char fpga_brdc_data;
void *fpga_enable;
void *fpga_polarity;
void *fpga_status;
void *fpga_trigger;
ppc4xx_setup_arch();
ibm_ocp_set_emac(0, 1);
kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
if (!kb_data) {
printk(KERN_CRIT
"sycamore_setup_arch() kb_data ioremap failed\n");
return;
}
kb_cs = kb_data + 1;
fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
if (!fpga_status) {
printk(KERN_CRIT
"sycamore_setup_arch() fpga_status ioremap failed\n");
return;
}
fpga_enable = fpga_status + 1;
fpga_polarity = fpga_status + 2;
fpga_trigger = fpga_status + 3;
fpga_brdc = fpga_status + 4;
/* split the keyboard and mouse interrupts */
fpga_brdc_data = readb(fpga_brdc);
fpga_brdc_data |= 0x80;
writeb(fpga_brdc_data, fpga_brdc);
writeb(0x3, fpga_enable);
writeb(0x3, fpga_polarity);
writeb(0x3, fpga_trigger);
/* RTC step for the sycamore */
sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
sycamore_rtc_base, 8);
ibm4xxPIC_InitSenses = Sycamore_IRQ_initsenses;
ibm4xxPIC_NumInitSenses = sizeof(Sycamore_IRQ_initsenses);
/* Identify the system */
printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
printk(KERN_INFO
"Port by MontaVista Software, Inc. ([email protected])\n");
}
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
* are non-zero, then we should use the board info from the bd_t
* structure and the cmdline pointed to by r6 instead of the
* information from birecs, if any. Otherwise, use the information
* from birecs as discovered by the preceeding call to
* parse_bootinfo(). This rule should work with both PPCBoot, which
* uses a bd_t board info structure, and the kernel boot wrapper,
* which uses birecs.
*/
if (r3 && r6) {
/* copy board info structure */
memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
/* copy command line */
*(char *)(r7+KERNELBASE) = 0;
strcpy(cmd_line, (char *)(r6+KERNELBASE));
}
#ifdef CONFIG_BLK_DEV_INITRD
/* take care of initrd if we have one */
if (r4) {
initrd_start = r4 + KERNELBASE;
initrd_end = r5 + KERNELBASE;
}
#endif /* CONFIG_BLK_DEV_INITRD */
/* Map in board regs, etc. */
sandpoint_set_bat();
isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
ISA_DMA_THRESHOLD = 0x00ffffff;
DMA_MODE_READ = 0x44;
DMA_MODE_WRITE = 0x48;
ppc_do_canonicalize_irqs = 1;
ppc_md.setup_arch = sandpoint_setup_arch;
ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
ppc_md.init_IRQ = sandpoint_init_IRQ;
ppc_md.get_irq = openpic_get_irq;
ppc_md.restart = sandpoint_restart;
ppc_md.power_off = sandpoint_power_off;
ppc_md.halt = sandpoint_halt;
ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
ppc_md.setup_io_mappings = sandpoint_map_io;
TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
ppc_md.time_init = todc_time_init;
ppc_md.set_rtc_time = todc_set_rtc_time;
ppc_md.get_rtc_time = todc_get_rtc_time;
ppc_md.calibrate_decr = todc_calibrate_decr;
ppc_md.nvram_read_val = todc_mc146818_read_val;
ppc_md.nvram_write_val = todc_mc146818_write_val;
#ifdef CONFIG_KGDB
ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = sandpoint_ide_default_irq;
ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
#endif
}
