/** * Detects stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus. * * @return * @retval false Bus is stuck. * @retval true Bus is clear. */ static bool twi_master_clear_bus(void) { bool bus_clear; TWI_SDA_HIGH() ; TWI_SCL_HIGH() ; TWI_DELAY(); if (TWI_SDA_READ() == 1 && TWI_SCL_READ() == 1) { bus_clear = true; } else { uint_fast8_t i; bus_clear = false; // Clock max 18 pulses worst case scenario(9 for master to send the rest of command and 9 for slave to respond) to SCL line and wait for SDA come high for (i = 18; i--;) { TWI_SCL_LOW() ; TWI_DELAY(); TWI_SCL_HIGH() ; TWI_DELAY(); if (TWI_SDA_READ() == 1) { bus_clear = true; break; } } } return bus_clear; }
/** * @brief Function for issuing TWI STOP condition to the bus. * * STOP condition is signaled by pulling SDA high while SCL is high. After this function SDA and SCL will be high. * * @return * @retval false Timeout detected * @retval true Clocking succeeded */ bool twi_master_issue_stopcondition(void) { #if 0 if (TWI_SCL_READ() == 1 && TWI_SDA_READ() == 1) { // Issue start, then issue stop // Pull SDA low to issue START TWI_SDA_LOW(); TWI_DELAY(); // Pull SDA high while SCL is high to issue STOP TWI_SDA_HIGH(); } else if (TWI_SCL_READ() == 1 && TWI_SDA_READ() == 0) { // Pull SDA high while SCL is high to issue STOP TWI_SDA_HIGH(); } else if (TWI_SCL_READ() == 0 && TWI_SDA_READ() == 0) { if (!twi_master_wait_while_scl_low()) { return false; } // Pull SDA high while SCL is high to issue STOP TWI_SDA_HIGH(); } else if (TWI_SCL_READ() == 0 && TWI_SDA_READ() == 1) { TWI_SDA_LOW(); TWI_DELAY(); // SCL high if (!twi_master_wait_while_scl_low()) { return false; } // Pull SDA high while SCL is high to issue STOP TWI_SDA_HIGH(); } TWI_DELAY(); #endif TWI_SDA_LOW(); TWI_DELAY(); if (!twi_master_wait_while_scl_low()) { return false; } TWI_SDA_HIGH(); TWI_DELAY(); return true; }
/** * @brief Function for clocking one data byte out and reads slave acknowledgment. * * Can handle clock stretching. * After calling this function SCL is low and SDA low/high depending on the * value of LSB of the data byte. * SCL is expected to be output and low when entering this function. * * @param databyte Data byte to clock out. * @return * @retval true Slave acknowledged byte. * @retval false Timeout or slave didn't acknowledge byte. */ bool twi_master_clock_byte(uint_fast8_t databyte) { bool transfer_succeeded = true; // Make sure SDA is an output TWI_SDA_OUTPUT(); // MSB first for (uint_fast8_t i = 0x80; i != 0; i>>=1) { TWI_SCL_LOW(); TWI_DELAY(); if (databyte & i) { TWI_SDA_HIGH(); } else { TWI_SDA_LOW(); } if (!twi_master_wait_while_scl_low()) { transfer_succeeded = false; // Timeout break; } } // Finish last data bit by pulling SCL low TWI_SCL_LOW(); TWI_DELAY(); // Configure TWI_SDA pin as input for receiving the ACK bit TWI_SDA_INPUT(); // Give some time for the slave to load the ACK bit on the line TWI_DELAY(); // Pull SCL high and wait a moment for SDA line to settle // Make sure slave is not stretching the clock transfer_succeeded &= twi_master_wait_while_scl_low(); // Read ACK/NACK. NACK == 1, ACK == 0 transfer_succeeded &= !(TWI_SDA_READ()); // Finish ACK/NACK bit clock cycle and give slave a moment to release control // of the SDA line TWI_SCL_LOW(); TWI_DELAY(); // Configure TWI_SDA pin as output as other module functions expect that TWI_SDA_OUTPUT(); return transfer_succeeded; }
/** * @brief Function for pulling SCL high and waits until it is high or timeout occurs. * * SCL is expected to be output before entering this function. * @note If TWI_MASTER_TIMEOUT_COUNTER_LOAD_VALUE is set to zero, timeout functionality is not compiled in. * @return * @retval true SCL is now high. * @retval false Timeout occurred and SCL is still low. */ bool twi_master_wait_while_scl_low(void) { #if TWI_MASTER_TIMEOUT_COUNTER_LOAD_VALUE != 0 uint32_t volatile timeout_counter = TWI_MASTER_TIMEOUT_COUNTER_LOAD_VALUE; #endif // Pull SCL high just in case if something left it low TWI_SCL_HIGH(); TWI_DELAY(); while (TWI_SCL_READ() == 0) { // If SCL is low, one of the slaves is busy and we must wait // nrf_delay_us(1); #if TWI_MASTER_TIMEOUT_COUNTER_LOAD_VALUE != 0 if (timeout_counter-- == 0) { // If timeout_detected, return false return false; } #endif } return true; }
/********************************************************************** name : function : return: 1--SUCCESS, 0--FAIL **********************************************************************/ bool TwoWire::twi_master_clear_bus(void) { bool bus_clear; uint32_t twi_state; uint32_t sck_pin_config; uint32_t sda_pin_config; twi_state = twi->ENABLE; twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; sck_pin_config = NRF_GPIO->PIN_CNF[SCL_Pin]; NRF_GPIO->PIN_CNF[SCL_Pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); sda_pin_config = NRF_GPIO->PIN_CNF[SDA_Pin]; NRF_GPIO->PIN_CNF[SDA_Pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_GPIO->OUTSET = ( 1 << SCL_Pin ); NRF_GPIO->OUTSET = ( 1 << SDA_Pin ); TWI_DELAY(4); if( ( (NRF_GPIO->IN >> SCL_Pin) & 0X1UL ) && ( (NRF_GPIO->IN >> SDA_Pin) & 0x1UL ) ) { bus_clear = 1; } else {
/** * @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus. * * @return * @retval false Bus is stuck. * @retval true Bus is clear. */ static bool twi_master_clear_bus(void) { uint32_t twi_state; bool bus_clear; uint32_t clk_pin_config; uint32_t data_pin_config; // Save and disable TWI hardware so software can take control over the pins. twi_state = NRF_TWI1->ENABLE; NRF_TWI1->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; clk_pin_config = \ NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER]; NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); data_pin_config = \ NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER]; NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \ (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); TWI_SDA_HIGH(); TWI_SCL_HIGH(); TWI_DELAY(); if ((TWI_SDA_READ() == 1) && (TWI_SCL_READ() == 1)) { bus_clear = true; } else { uint_fast8_t i; bus_clear = false; // Clock max 18 pulses worst case scenario(9 for master to send the rest of command and 9 // for slave to respond) to SCL line and wait for SDA come high. for (i=18; i--;) { TWI_SCL_LOW(); TWI_DELAY(); TWI_SCL_HIGH(); TWI_DELAY(); if (TWI_SDA_READ() == 1) { bus_clear = true; break; } } } NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = clk_pin_config; NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = data_pin_config; NRF_TWI1->ENABLE = twi_state; return bus_clear; }
/** * @brief Function for clocking one data byte in and sends ACK/NACK bit. * * Can handle clock stretching. * SCL is expected to be output and low when entering this function. * After calling this function, SCL is high and SDA low/high depending if ACK/NACK was sent. * * @param databyte Data byte to clock out. * @param ack If true, send ACK. Otherwise send NACK. * @return * @retval true Byte read succesfully * @retval false Timeout detected */ bool twi_master_clock_byte_in(uint8_t *databyte, bool ack) { uint_fast8_t byte_read = 0; bool transfer_succeeded = true; // Make sure SDA is an input TWI_SDA_INPUT(); // SCL state is guaranteed to be high here // MSB first for (uint_fast8_t i = 0x80; i != 0; i>>=1) { if (!twi_master_wait_while_scl_low()) { transfer_succeeded = false; break; } if (TWI_SDA_READ()) { byte_read |= i; } else { // No need to do anything } TWI_SCL_LOW(); TWI_DELAY(); } // Make sure SDA is an output before we exit the function TWI_SDA_OUTPUT(); *databyte = (uint8_t)byte_read; // Send ACK bit // SDA high == NACK, SDA low == ACK if (ack) { TWI_SDA_LOW(); } else { TWI_SDA_HIGH(); } // Let SDA line settle for a moment TWI_DELAY(); // Drive SCL high to start ACK/NACK bit transfer // Wait until SCL is high, or timeout occurs if (!twi_master_wait_while_scl_low()) { transfer_succeeded = false; // Timeout } // Finish ACK/NACK bit clock cycle and give slave a moment to react TWI_SCL_LOW(); TWI_DELAY(); return transfer_succeeded; }
/** * @brief Function for issuing TWI START condition to the bus. * * START condition is signaled by pulling SDA low while SCL is high. After this function SCL and SDA will be low. * * @return * @retval false Timeout detected * @retval true Clocking succeeded */ bool twi_master_issue_startcondition(void) { #if 0 if (TWI_SCL_READ() == 1 && TWI_SDA_READ() == 1) { // Pull SDA low TWI_SDA_LOW(); } else if (TWI_SCL_READ() == 1 && TWI_SDA_READ() == 0) { // Issue Stop by pulling SDA high TWI_SDA_HIGH(); TWI_DELAY(); // Then Start by pulling SDA low TWI_SDA_LOW(); } else if (TWI_SCL_READ() == 0 && TWI_SDA_READ() == 0) { // First pull SDA high TWI_SDA_HIGH(); // Then SCL high if (!twi_master_wait_while_scl_low()) { return false; } // Then SDA low TWI_SDA_LOW(); } else if (TWI_SCL_READ() == 0 && TWI_SDA_READ() == 1) { // SCL high if (!twi_master_wait_while_scl_low()) { return false; } // Then SDA low TWI_SDA_LOW(); } TWI_DELAY(); TWI_SCL_LOW(); #endif // Make sure both SDA and SCL are high before pulling SDA low. TWI_SDA_HIGH(); TWI_DELAY(); if (!twi_master_wait_while_scl_low()) { return false; } TWI_SDA_LOW(); TWI_DELAY(); // Other module function expect SCL to be low TWI_SCL_LOW(); TWI_DELAY(); return true; }