/**
* @brief This Function flushes the FIFOs.
* @param pdev: device instance
* @param epnum: endpoint address
* @retval : status
*/
uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
{
if ((epnum & 0x80) == 0x80)
{
USB_OTG_FlushTxFifo(pdev, epnum & 0x7F);
}
else
{
USB_OTG_FlushRxFifo(pdev);
}
return (0);
}
//--------------------------------------------------------------
void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE * pdev)
{
uint32_t i;
pdev->dev.device_status = 1;
for (i = 0; i < pdev->cfg.dev_endpoints; i++) {
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
}
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DIEPMSK, 0);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DOEPMSK, 0);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DAINTMSK, 0);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DAINT, 0xFFFFFFFF);
/* Flush the FIFO */
USB_OTG_FlushRxFifo(pdev);
USB_OTG_FlushTxFifo(pdev, 0x10);
}
//--------------------------------------------------------------
void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_HCCHAR_TypeDef hcchar;
uint32_t i;
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0);
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF);
/* Flush out any leftover queued requests. */
for (i = 0; i < pdev->cfg.host_channels; i++)
{
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
hcchar.b.chen = 0;
hcchar.b.chdis = 1;
hcchar.b.epdir = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32);
}
/* Flush the FIFO */
USB_OTG_FlushRxFifo(pdev);
USB_OTG_FlushTxFifo(pdev , 0x10 );
}
//--------------------------------------------------------------
USB_OTG_STS USB_OTG_CoreInitDev(USB_OTG_CORE_HANDLE * pdev)
{
USB_OTG_STS status = USB_OTG_OK;
USB_OTG_DEPCTL_TypeDef depctl;
uint32_t i;
USB_OTG_DCFG_TypeDef dcfg;
USB_OTG_FSIZ_TypeDef nptxfifosize;
USB_OTG_FSIZ_TypeDef txfifosize;
USB_OTG_DIEPMSK_TypeDef msk;
USB_OTG_DTHRCTL_TypeDef dthrctl;
depctl.d32 = 0;
dcfg.d32 = 0;
nptxfifosize.d32 = 0;
txfifosize.d32 = 0;
msk.d32 = 0;
/* Restart the Phy Clock */
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
/* Device configuration register */
dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG);
dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80;
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32);
if (pdev->cfg.coreID == USB_OTG_FS_CORE_ID) {
/* Set Full speed phy */
USB_OTG_InitDevSpeed(pdev, USB_OTG_SPEED_PARAM_FULL);
/* set Rx FIFO size */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE);
/* EP0 TX */
nptxfifosize.b.depth = TX0_FIFO_FS_SIZE;
nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
/* EP1 TX */
txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth;
txfifosize.b.depth = TX1_FIFO_FS_SIZE;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32);
/* EP2 TX */
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.depth = TX2_FIFO_FS_SIZE;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32);
/* EP3 TX */
txfifosize.b.startaddr += txfifosize.b.depth;
txfifosize.b.depth = TX3_FIFO_FS_SIZE;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32);
}
/* Flush the FIFOs */
USB_OTG_FlushTxFifo(pdev, 0x10); /* all Tx FIFOs */
USB_OTG_FlushRxFifo(pdev);
/* Clear all pending Device Interrupts */
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DIEPMSK, 0);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DOEPMSK, 0);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DAINT, 0xFFFFFFFF);
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DAINTMSK, 0);
for (i = 0; i < pdev->cfg.dev_endpoints; i++) {
depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL);
if (depctl.b.epena) {
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
} else {
depctl.d32 = 0;
}
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32);
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0);
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
}
for (i = 0; i < pdev->cfg.dev_endpoints; i++) {
USB_OTG_DEPCTL_TypeDef depctl;
depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL);
if (depctl.b.epena) {
depctl.d32 = 0;
depctl.b.epdis = 1;
depctl.b.snak = 1;
} else {
depctl.d32 = 0;
}
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32);
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0);
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
}
msk.d32 = 0;
msk.b.txfifoundrn = 1;
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32);
if (pdev->cfg.dma_enable == 1) {
dthrctl.d32 = 0;
dthrctl.b.non_iso_thr_en = 1;
dthrctl.b.iso_thr_en = 1;
dthrctl.b.tx_thr_len = 64;
dthrctl.b.rx_thr_en = 1;
dthrctl.b.rx_thr_len = 64;
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32);
}
USB_OTG_EnableDevInt(pdev);
return status;
}
//--------------------------------------------------------------
USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev)
{
USB_OTG_STS status = USB_OTG_OK;
USB_OTG_FSIZ_TypeDef nptxfifosize;
USB_OTG_FSIZ_TypeDef ptxfifosize;
USB_OTG_HCFG_TypeDef hcfg;
uint32_t i = 0;
nptxfifosize.d32 = 0;
ptxfifosize.d32 = 0;
hcfg.d32 = 0;
/* configure charge pump IO */
USB_OTG_BSP_ConfigVBUS(pdev);
/* Restart the Phy Clock */
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0);
/* Initialize Host Configuration Register */
if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)
{
USB_OTG_InitFSLSPClkSel(pdev , HCFG_30_60_MHZ);
}
else
{
USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ);
}
USB_OTG_ResetPort(pdev);
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
hcfg.b.fslssupp = 0;
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32);
/* Configure data FIFO sizes */
/* Rx FIFO */
if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID)
{
/* set Rx FIFO size */
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE);
nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE;
nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32);
ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ;
ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ;
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32);
}
/* Make sure the FIFOs are flushed. */
USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */
USB_OTG_FlushRxFifo(pdev);
/* Clear all pending HC Interrupts */
for (i = 0; i < pdev->cfg.host_channels; i++)
{
USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF );
USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINTMSK, 0 );
}
USB_OTG_DriveVbus(pdev, 1);
USB_OTG_EnableHostInt(pdev);
return status;
}
