void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
assert(uart <= UART_NUMOF && uart != 0);
while(len--) {
while(UxSTA(pic_uart[uart])& _U1STA_UTXBF_MASK) {}
UxTXREG(pic_uart[uart]) = *data++;
}
}
void uart_read(unsigned int uart_num, void *buffer, uint32_t length)
{
uint8_t *data = (uint8_t *)buffer;
uint8_t *end = data + length;
while (data != end) {
while (!(UxSTA(uart_num) & _U1STA_URXDA_MASK))
;
*data++ = UxRXREG(uart_num);
}
}
void uart_write(unsigned int uart_num, const void *buffer, uint32_t length)
{
const uint8_t *data = (const uint8_t *)buffer;
const uint8_t *end = data + length;
while (data != end) {
/* Wait until there is some space in TX FIFO */
while (UxSTA(uart_num) & _U1STA_UTXBF_MASK)
;
UxTXREG(uart_num) = *data++;
}
}
uint32_t uart_read_noblock(unsigned int uart_num, void *buffer, uint32_t length)
{
uint8_t *data = (uint8_t *)buffer;
uint32_t byte_read_count = 0;
while (byte_read_count < length) {
if (UxSTA(uart_num) & _U1STA_URXDA_MASK)
data[byte_read_count] = UxRXREG(uart_num);
else
break;
}
return byte_read_count;
}
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
assert(uart <= UART_NUMOF && uart != 0); /*No uart 0 on pic32*/
/* Pin Mux should be setup in board file */
pic_uart[uart].regs =
(volatile uint32_t *)(_UART1_BASE_ADDRESS + (uart - 1) * REGS_SPACING);
pic_uart[uart].clock = PERIPHERAL_CLOCK;
UxBRG(pic_uart[uart])= (pic_uart[uart].clock / (16 * baudrate)) - 1;
UxSTA(pic_uart[uart])= 0;
UxMODE(pic_uart[uart])= _U1MODE_ON_MASK;
UxSTASET(pic_uart[uart])= _U1STA_URXEN_MASK;
UxSTASET(pic_uart[uart])= _U1STA_UTXEN_MASK;
return 0;
}
int uart_configure(unsigned int uart_num, uint32_t baudrate)
{
UxMODE(uart_num) = 0;
UxSTA(uart_num) = 0;
return compute_divisor(uart_num, baudrate);
}
void uart_disable(unsigned int uart_num)
{
UxMODE(uart_num) &= ~_U1MODE_UARTEN_MASK;
UxSTA(uart_num) &= ~(_U1STA_URXEN_MASK | _U1STA_UTXEN_MASK);
}
void uart_enable(unsigned int uart_num)
{
UxMODE(uart_num) |= _U1MODE_UARTEN_MASK;
UxSTA(uart_num) |= _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
}