void rk3288_vpu_vp8e_run(struct rk3288_vpu_ctx *ctx)
{
struct rk3288_vpu_dev *vpu = ctx->dev;
u32 reg;
/* The hardware expects the control buffer to be zeroed. */
memset(ctx->hw.vp8e.ctrl_buf.cpu, 0,
sizeof(struct rk3288_vpu_vp8e_ctrl_buf));
/*
* Program the hardware.
*/
rk3288_vpu_power_on(vpu);
vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_VP8,
VEPU_REG_ENC_CTRL);
rk3288_vpu_vp8e_set_params(vpu, ctx);
rk3288_vpu_vp8e_set_buffers(vpu, ctx);
/* Make sure that all registers are written at this point. */
wmb();
/* Set the watchdog. */
schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
/* Start the hardware. */
reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
| VEPU_REG_AXI_CTRL_INPUT_SWAP16
| VEPU_REG_AXI_CTRL_BURST_LEN(16)
| VEPU_REG_AXI_CTRL_GATE_BIT
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
| VEPU_REG_AXI_CTRL_INPUT_SWAP32
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
| VEPU_REG_AXI_CTRL_INPUT_SWAP8;
vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
reg = VEPU_REG_ENC_CTRL_NAL_MODE_BIT
| VEPU_REG_ENC_CTRL_WIDTH(MB_WIDTH(ctx->src_fmt.width))
| VEPU_REG_ENC_CTRL_HEIGHT(MB_HEIGHT(ctx->src_fmt.height))
| VEPU_REG_ENC_CTRL_ENC_MODE_VP8
| VEPU_REG_ENC_CTRL_EN_BIT;
if (ctx->run.dst->b.v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME)
reg |= VEPU_REG_ENC_CTRL_KEYFRAME_BIT;
vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
}
void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct vb2_buffer *src_buf, *dst_buf;
struct rockchip_vpu_jpeg_ctx jpeg_ctx;
u32 reg;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
memset(&jpeg_ctx, 0, sizeof(jpeg_ctx));
jpeg_ctx.buffer = vb2_plane_vaddr(dst_buf, 0);
jpeg_ctx.width = ctx->dst_fmt.width;
jpeg_ctx.height = ctx->dst_fmt.height;
jpeg_ctx.quality = ctx->jpeg_quality;
rockchip_vpu_jpeg_header_assemble(&jpeg_ctx);
/* Switch to JPEG encoder mode before writing registers */
vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_JPEG,
VEPU_REG_ENC_CTRL);
rk3288_vpu_set_src_img_ctrl(vpu, ctx);
rk3288_vpu_jpeg_enc_set_buffers(vpu, ctx, src_buf);
rk3288_vpu_jpeg_enc_set_qtable(vpu,
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0),
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1));
reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
| VEPU_REG_AXI_CTRL_INPUT_SWAP16
| VEPU_REG_AXI_CTRL_BURST_LEN(16)
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
| VEPU_REG_AXI_CTRL_INPUT_SWAP32
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
| VEPU_REG_AXI_CTRL_INPUT_SWAP8;
/* Make sure that all registers are written at this point. */
vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
reg = VEPU_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
| VEPU_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
| VEPU_REG_ENC_CTRL_ENC_MODE_JPEG
| VEPU_REG_ENC_PIC_INTRA
| VEPU_REG_ENC_CTRL_EN_BIT;
/* Kick the watchdog and start encoding */
schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
}