static void rk3399_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
u32 reg;
/*
* The pix fmt width/height are already macroblock aligned
* by .vidioc_s_fmt_vid_cap_mplane() callback
*/
reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width);
vepu_write_relaxed(vpu, reg, VEPU_REG_INPUT_LUMA_INFO);
reg = VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0) |
VEPU_REG_IN_IMG_CTRL_OVRFLB(0);
/*
* This register controls the input crop, as the offset
* from the right/bottom within the last macroblock. The offset from the
* right must be divided by 4 and so the crop must be aligned to 4 pixels
* horizontally.
*/
vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET);
reg = VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1);
}
static void rk3288_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
u32 reg;
reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
| VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0)
| VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(0)
| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
vepu_write_relaxed(vpu, reg, VEPU_REG_IN_IMG_CTRL);
}
static inline u32 enc_in_img_ctrl(struct rk3288_vpu_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
struct v4l2_rect *crop = &ctx->src_crop;
unsigned bytes_per_line, overfill_r, overfill_b;
/*
* The hardware needs only the value for luma plane, because
* values of other planes are calculated internally based on
* format setting.
*/
bytes_per_line = pix_fmt->plane_fmt[0].bytesperline;
overfill_r = (pix_fmt->width - crop->width) / 4;
overfill_b = pix_fmt->height - crop->height;
return VEPU_REG_IN_IMG_CTRL_ROW_LEN(bytes_per_line)
| VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r)
| VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(overfill_b)
| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
}
