// ------------------------------------------------------- QString JK_FlipFlop::vhdlCode(int NumPorts) { QString s = ""; if(NumPorts <= 0) { // no truth table simulation ? QString td = Props.at(0)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format s += td; } s += ";\n"; s = " " + Name + " : process (" + Ports.at(5)->Connection->Name + ", " + Ports.at(6)->Connection->Name + ", " + Ports.at(4)->Connection->Name + ")\n begin\n if (" + Ports.at(6)->Connection->Name + "='1') then " + Ports.at(2)->Connection->Name + " <= '0'" + s +" elsif (" + Ports.at(5)->Connection->Name + "='1') then " + Ports.at(2)->Connection->Name + " <= '1'" + s +" elsif (" + Ports.at(4)->Connection->Name + "='1' and " + Ports.at(4)->Connection->Name + "'event) then\n " + Ports.at(2)->Connection->Name + " <= (" + Ports.at(0)->Connection->Name + " and not " + Ports.at(2)->Connection->Name + ") or (not " + Ports.at(1)->Connection->Name + " and " + Ports.at(2)->Connection->Name + ")" + s + " end if;\n end process;\n " + Ports.at(3)->Connection->Name + " <= not " + Ports.at(2)->Connection->Name + ";\n\n"; return s; }
QString andor4x2::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString a11 = Ports.at(0)->Connection->Name; QString a12 = Ports.at(1)->Connection->Name; QString a21 = Ports.at(2)->Connection->Name; QString a22 = Ports.at(3)->Connection->Name; QString a31 = Ports.at(4)->Connection->Name; QString a32 = Ports.at(5)->Connection->Name; QString a41 = Ports.at(6)->Connection->Name; QString a42 = Ports.at(7)->Connection->Name; QString y = Ports.at(8)->Connection->Name; s = "\n " + Name +":process ("+a11+", "+a12+", "+a21+", "+ a22+", "+ a31+", "+a32+", "+a41+", "+a42 + ")\n"+ " begin\n " + y+" <= "+"("+a11+" and "+a12+") or "+"("+a21+" and "+a22+") or "+ "\n ("+a31+" and " +a32+") or "+ "("+a41+" and "+a42+")"+td+ " end process;\n"; return s; }
QString dff_SR::vhdlCode( int ) { QString s=""; QString td = Props.at(2)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString S = Ports.at(0)->Connection->Name; QString D = Ports.at(1)->Connection->Name; QString CLK = Ports.at(2)->Connection->Name; QString R = Ports.at(3)->Connection->Name; QString QB = Ports.at(4)->Connection->Name; QString Q = Ports.at(5)->Connection->Name; s = "\n "+Name+":process ("+S+", "+CLK+", "+R+") is\n"+ " variable state : std_logic;\n"+ " begin\n" + " if ("+S+" = '0') then\n"+ " state := '1';\n"+ " elsif ("+R+" = '0') then\n"+ " state := '0';\n"+ " elsif ("+CLK+" = '1' and "+CLK+"'event) then\n"+ " state := "+D+";\n"+ " end if;\n"+ " "+Q+" <= state"+td+ " "+QB+" <= not state"+td+ " end process;\n"; return s; }
QString mux4to1::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString En = Ports.at(0)->Connection->Name; QString A = Ports.at(1)->Connection->Name; QString B = Ports.at(2)->Connection->Name; QString D0 = Ports.at(3)->Connection->Name; QString D1 = Ports.at(4)->Connection->Name; QString D2 = Ports.at(5)->Connection->Name; QString D3 = Ports.at(6)->Connection->Name; QString y = Ports.at(7)->Connection->Name; s = "\n " + Name + ":process (" + En + ", " + A + ", " + B + ", " + D0 + ", " + D1 + ", " + D2 + ", " + D3 + ")\n" + " begin\n " + y + " <= " + "(not " + En + ") and ((" + D3 + " and " + B + " and " + A + ") or\n" + " (" + D2 + " and " + B + " and not " + A + ") or\n" + " (" + D1 + " and not " + B + " and " + A + ") or\n" + " (" + D0 + " and not " + B + " and not " + A + ")" + ")" + td + " end process;\n"; return s; }
QString fa2b::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString D = Ports.at(0)->Connection->Name; QString C = Ports.at(1)->Connection->Name; QString B = Ports.at(2)->Connection->Name; QString A = Ports.at(3)->Connection->Name; QString E = Ports.at(4)->Connection->Name; QString CO = Ports.at(5)->Connection->Name; QString S1 = Ports.at(6)->Connection->Name; QString S0 = Ports.at(7)->Connection->Name; s = "\n "+Name+":process ("+A+", "+B+", "+C+", "+D+", "+E+ ")\n"+ " begin\n" + " "+CO+" <= ("+A+" and "+C+") or (("+A+" or "+C+") and (("+B+" and "+D+") or ("+E+" and "+B+") or ("+E+" and "+ D +")))"+td+ " "+S1+" <= (("+B+" and "+D+") or ("+E+" and "+B+") or ("+E+" and "+D+"))"+" xor ("+A+" xor "+C+")"+td+ " "+S0+" <= "+E+" xor ("+B+" xor "+D+")"+td+ " end process;\n"; return s; }
// ------------------------------------------------------- QString Logical_Buf::vhdlCode(int NumPorts) { QString s = " " + Ports.first()->Connection->Name + " <= " + Ports.last()->Connection->Name; if(NumPorts <= 0) { // no truth table simulation ? QString td = Props.at(1)->Value; if(!VHDL_Delay(td, Name)) return td; s += td; } s += ";\n"; return s; }
// ------------------------------------------------------- QString RS_FlipFlop::vhdlCode(int NumPorts) { QString s = ""; if(NumPorts <= 0) { // no truth table simulation ? QString td = Props.at(0)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format s = td; } s += ";\n"; s = " " + Ports.at(2)->Connection->Name + " <= " + Ports.at(0)->Connection->Name + " nor " + Ports.at(3)->Connection->Name + s + " " + Ports.at(3)->Connection->Name + " <= " + Ports.at(1)->Connection->Name + " nor " + Ports.at(2)->Connection->Name + s + '\n'; return s; }
// ------------------------------------------------------- QString Digi_Source::vhdlCode(int NumPorts) { QString s, t; QString Out(" " + Ports.getFirst()->Connection->Name + " <= '"); s = "\n " + Name + ":process\n begin\n"; int z = 0; char State; if(NumPorts <= 0) { // time table simulation ? if(Props.at(0)->Value == "low") State = '0'; else State = '1'; t = Props.at(2)->Value.section(';',z,z).stripWhiteSpace(); while(!t.isEmpty()) { s += Out + State + "';"; // next value for signal if(!VHDL_Delay(t, Name)) return t; // time has not VHDL format s += t.replace("after","wait for") + ";\n"; State ^= 1; z++; t = Props.at(2)->Value.section(';',z,z).stripWhiteSpace(); } } else { // truth table simulation State = '0'; int Num = Props.at(0)->Value.toInt() - 1; s += Out + State + "';"; // first value for signal s += " wait for "+QString::number(1 << Num)+" ns;\n"; State ^= 1; s += Out + State + "';"; // next value for signal s += " wait for "+QString::number(1 << Num)+" ns;\n"; } s += " end process;\n"; return s; }
QString ha1b::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString A = Ports.at(0)->Connection->Name; QString B = Ports.at(1)->Connection->Name; QString CO = Ports.at(2)->Connection->Name; QString S = Ports.at(3)->Connection->Name; s = "\n " + Name + ":process (" + A + ", " + B + ")\n" + " begin\n" + " " + CO + " <= " + A + " and " + B + td + " " + S + " <= " + A + " xor " + B + td + " end process;\n"; return s; }
QString comp_4bit::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString X0 = Ports.at(0)->Connection->Name; QString X1 = Ports.at(1)->Connection->Name; QString X2 = Ports.at(2)->Connection->Name; QString X3 = Ports.at(3)->Connection->Name; QString Y0 = Ports.at(4)->Connection->Name; QString Y1 = Ports.at(5)->Connection->Name; QString Y2 = Ports.at(6)->Connection->Name; QString Y3 = Ports.at(7)->Connection->Name; QString L = Ports.at(8)->Connection->Name; QString G = Ports.at(9)->Connection->Name; QString E = Ports.at(10)->Connection->Name; s = "\n "+Name+":process ("+X0+", "+X1+", "+X2+", "+X3+", "+Y0+", "+Y1+", "+Y2+", "+Y3+")\n"+ " variable P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11 : std_logic;\n"+ " begin\n"+ " P0 := not ("+X0+" xor "+Y0+");\n"+ " P1 := not ("+X1+" xor "+Y1+");\n"+ " P2 := not ("+X2+" xor "+Y2+");\n"+ " P3 := not ("+X3+" xor "+Y3+");\n"+ " P4 := (not "+X0+") and "+Y0+";\n"+ " P5 := (not "+X1+") and "+Y1+";\n"+ " P6 := (not "+X2+") and "+Y2+";\n"+ " P7 := (not "+X3+") and "+Y3+";\n"+ " P8 := "+X0+" and (not "+Y0+");\n"+ " P9 := "+X1+" and (not "+Y1+");\n"+ " P10 := "+X2+" and (not "+Y2+");\n"+ " P11 := "+X3+" and (not "+Y3+");\n"+ " "+L+" <= P7 or (P3 and P6) or (P3 and P2 and P5) or (P3 and P2 and P1 and P4)"+td+ " "+G+" <= P11 or (P3 and P10) or (P3 and P2 and P9) or (P3 and P2 and P1 and P8)"+td+ " "+E+" <= P3 and P2 and P1 and P0"+td+ " end process;\n"; return s; }
QString mux2to1::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; if(!VHDL_Delay(td, Name)) return td; // Time does not have VHDL format. td += ";\n"; QString En = Ports.at(0)->Connection->Name; QString A = Ports.at(1)->Connection->Name; QString D0 = Ports.at(2)->Connection->Name; QString D1 = Ports.at(3)->Connection->Name; QString y = Ports.at(4)->Connection->Name; s = "\n " + Name + ":process (" + En + ", " + A + ", " + D0 + ", " + D1 + ")\n" + " begin\n" + " " + y + " <= " + "(not " + En + ") and ((" + D1 + " and " + A + ") or " + "(" + D0 + " and " + "(not " + A + ")))" + td + " end process;\n"; return s; }
QString comp_1bit::vhdlCode( int ) { QString s=""; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString X = Ports.at(0)->Connection->Name; QString Y = Ports.at(1)->Connection->Name; QString L = Ports.at(2)->Connection->Name; QString G = Ports.at(3)->Connection->Name; QString E = Ports.at(4)->Connection->Name; s = "\n "+Name+":process ("+X+", "+Y+")\n"+ " begin\n"+ " "+L+" <= (not "+X+") and "+Y+td+ " "+G+" <= "+X+" and (not "+Y+")"+td+ " "+E+" <= not ("+X+" xor "+Y+")"+td+ " end process;\n"; return s; }
QString gatedDlatch::vhdlCode( int ) { QString s=""; QString td = Props.at(2)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString D = Ports.at(0)->Connection->Name; QString C = Ports.at(1)->Connection->Name; QString QB = Ports.at(2)->Connection->Name; QString Q = Ports.at(3)->Connection->Name; s = "\n "+Name+":process ("+D+", "+C+")\n"+ " begin\n" + " if ("+C+" = '1') then\n"+ " "+Q+" <= "+D+td+ " "+QB+" <= not "+D+td+ " end if;\n"+ " end process;\n"; return s; }
QString hpribin4bit::vhdlCode( int ) { QString s; QString td = Props.at(1)->Value; // delay time if(!VHDL_Delay(td, Name)) return td; // time has not VHDL format td += ";\n"; QString A = Ports.at(0)->Connection->Name; QString B = Ports.at(1)->Connection->Name; QString C = Ports.at(2)->Connection->Name; QString D = Ports.at(3)->Connection->Name; QString V = Ports.at(4)->Connection->Name; QString Y = Ports.at(5)->Connection->Name; QString X = Ports.at(6)->Connection->Name; s = "\n "+Name+":process ("+A+", "+B+", "+C+", "+D+")\n"+ " begin\n" + " "+X+" <= "+D+" or "+C+td+ " "+Y+" <= "+D+" or ((not "+C+") and "+B+")"+td+ " "+V+" <= "+D+" or "+C+" or "+B+" or "+A+td+ " end process;\n"; return s; }