static void HwGpioSetMode(uint8 mode){
if(isRT63365)
VPint(0xbfb00860) &=~((1<<9)|(1<<12));//>63365 GPIO 7 and 10 share use for enthnet LED
if (mode == MDIO_READ){
// set gpio10 as output pin
//VPint(CR_GPIO_CTRL) |= (1<<(10*2));
//VPint(CR_GPIO_ODRAIN) |= (1<<10);
#if 0
// set gpio7 as input pin
VPint(CR_GPIO_ODRAIN) &= ~(1<<7);
VPint(CR_GPIO_CTRL) &= ~(1<<(7*2));
#else
GPIO_IEN(mdio_gpio);
#endif
}
else if (mode == MDIO_WRITE){
#if 0
// set gpio7/10 as output pin
VPint(CR_GPIO_CTRL) |= (1<<(7*2))|(1<<(10*2));
VPint(CR_GPIO_ODRAIN) |= (1<<7)|(1<<(10));
#else
GPIO_OEN(mdio_gpio);
GPIO_OEN(mdc_gpio);
#endif
}
}
static void tc3162_timer_ack(void)
{
uint32 word;
word = VPint(CR_TIMER_CTL);
word &= 0xffc0ffff;
word |= 0x00020000;
VPint(CR_TIMER_CTL) = word;
}
void __cpuinit spram_config(void)
{
struct cpuinfo_mips *c = ¤t_cpu_data;
unsigned int config0;
switch (c->cputype) {
case CPU_24K:
case CPU_34K:
case CPU_74K:
case CPU_1004K:
config0 = read_c0_config();
/* FIXME: addresses are Malta specific */
#ifdef CONFIG_MIPS_TC3262
#ifdef CONFIG_TC3162_IMEM
if (config0 & (1<<24)) {
probe_spram("ISPRAM", CPHYSADDR(&__imem),
&ispram_load_tag, &ispram_store_tag);
ispram_fill();
if (!isRT63165 && !isRT63365 && !isMT751020)
VPint(CR_DMC_ISPCFGR) = (CPHYSADDR(&__imem) & 0xfffff000) | (1<<8) | (0x7);
}
#endif
#ifdef CONFIG_TC3162_DMEM
if (isRT63165 || isRT63365) {
VPint(CR_SRAM) = (CPHYSADDR(DSPRAM_BASE) & 0xffffc000) | (1<<0);
printk(KERN_INFO "Enable SRAM=0x%08lx\n", VPint(CR_SRAM));
sram_allocp = (char *) CKSEG1ADDR(DSPRAM_BASE);
sram_size = sram_free = 0x8000;
} else {
if (!isTC3182 && !isRT65168) {
if (config0 & (1<<23)) {
if(isMT751020){
probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE),
&dspram_load_tag, &dspram_store_tag);
dspram_p = (char *)(DSPRAM_BASE);
}
else{
probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE),
&dspram_load_tag, &dspram_store_tag);
VPint(CR_DMC_DSPCFGR) = (CPHYSADDR(DSPRAM_BASE) & 0xfffff000) | (1<<8) | (0x7);
}
}
}
}
#endif
#else
if (config0 & (1<<24)) {
probe_spram("ISPRAM", 0x1c000000,
&ispram_load_tag, &ispram_store_tag);
}
if (config0 & (1<<23))
probe_spram("DSPRAM", 0x1c100000,
&dspram_load_tag, &dspram_store_tag);
#endif
}
}
void
timer_WatchDogConfigure (
uint8 tick_enable,
uint8 watchdog_enable
)
{
uint32 word;
word = VPint(CR_TIMER_CTL);
word &= 0xfdffffdf;
word |= ( tick_enable << 5)|(watchdog_enable<<25);
VPint (CR_TIMER_CTL)=word;
}
void
timer_Configure(
uint8 timer_no,
uint8 timer_enable,
uint8 timer_mode,
uint8 timer_halt
)
{
uint32 word,word1;
word = VPint(CR_TIMER_CTL);
word1 = (timer_enable << timer_no)|(timer_mode << (timer_no + 8))|(timer_halt << (timer_no + 26));
word |= word1;
VPint (CR_TIMER_CTL)=word;
}
void tc3162_disable_irq(unsigned int irq)
{
#ifdef CONFIG_MIPS_TC3262
unsigned long flags;
spin_lock_irqsave(&tc3162_irq_lock, flags);
if (irq <= 32)
VPint(CR_INTC_IMR) &= ~(1 << (irq-1));
else
VPint(CR_INTC_IMR_1) &= ~(1 << (irq-33));
spin_unlock_irqrestore(&tc3162_irq_lock, flags);
#else
VPint(CR_INTC_IMR) &= ~(1 << (irq-1));
#endif
}
static void delay1ms(int ms)
{
volatile uint32 timer_now, timer_last;
volatile uint32 tick_acc;
uint32 one_tick_unit = 1 * SYS_HCLK * 1000 / 2;
volatile uint32 tick_wait = ms * one_tick_unit;
volatile uint32 timer1_ldv = VPint(CR_TIMER1_LDV);
tick_acc = 0;
timer_last = VPint(CR_TIMER1_VLR);
do {
timer_now = VPint(CR_TIMER1_VLR);
if (timer_last >= timer_now)
tick_acc += timer_last - timer_now;
else
tick_acc += timer1_ldv - timer_now + timer_last;
timer_last = timer_now;
} while (tick_acc < tick_wait);
}
void osTimerInterruptInitialize(void)
{
/* ************ BEGIN TARGET SPECIFIC SECTION **************/
TimerInterval(0);
(VPint(TDATA(0))) = gBUSCLK/100;
TimerStart(0);
Enable_Int(TIMER0_INT);
/* ************ END TARGET SPECIFIC SECTION **************/
}
__IMEM asmlinkage void plat_irq_dispatch(void)
{
#ifdef CONFIG_MIPS_TC3262
int irq = ((read_c0_cause() & ST0_IM) >> 10);
do_IRQ(irq);
#else
do_IRQ(VPint(CR_INTC_IVR));
#endif
}
/*_____________________________________________________________________________
** function name: SLIC_reset
** descriptions:
** Reset or enable two SLIC devices
** parameters:
** reset: Identify the type of the operation to be performed
** global:
** None
** return:
** None
** call:
** None
** revision:
** 1.1 2008/09/26 14:30 Ian
**____________________________________________________________________________
*/
void SLIC_reset(int reset)
{
u32 gpio_dir_reg = RALINK_PIO_BASE+0x0;
u32 gpio_data_reg = RALINK_PIO_BASE+0x20;
u32 gpio_offset = CONFIG_RALINK_PCMRST_GPIO;
u32 reg;
if (SLIC1_GPIO > 31)
{
gpio_dir_reg = RALINK_PIO_BASE+0x4;
gpio_data_reg = RALINK_PIO_BASE+0x24;
gpio_offset -= 32;
}
reg = VPint(gpio_dir_reg);
reg |= (1<<gpio_offset); /* set GPIO#0 as output pin */
VPint(gpio_dir_reg) = reg;
if (reset == RESET){
reg = VPint(gpio_data_reg);
reg &= (~1<<gpio_offset); /* set GPIO#0 as low */
VPint(gpio_data_reg) = reg;
}
else{
reg = VPint(gpio_data_reg);
reg |= (1<<gpio_offset); /* set GPIO#0 as high */
VPint(gpio_data_reg) = reg;
}
if (reset == RESET)
{
gpio_dir_reg = RALINK_PIO_BASE+0x0;
gpio_data_reg = RALINK_PIO_BASE+0x20;
gpio_offset = SLIC1_GPIO;
reg = VPint(gpio_dir_reg);
reg |= (1<<gpio_offset); /* set SPI_CS1 as output pin */
VPint(gpio_dir_reg) = reg;
reg = VPint(gpio_data_reg);
reg |= (1<<gpio_offset); /* set SPI_CS1 as HIGH */
VPint(gpio_data_reg) = reg;
}
}
static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
{
unsigned int vpflags = dvpe();
int cpu_irq = 0;
if ((irq == SI_SWINT1_INT1) || (irq == SI_SWINT_INT1))
cpu_irq = 1;
VPint(CR_INTC_IMR) |= (1 << (irq-1));
if (irq == SI_SWINT_INT0)
VPint(CR_INTC_IMR) |= (1 << (SI_SWINT1_INT0-1));
else if (irq == SI_SWINT_INT1)
VPint(CR_INTC_IMR) |= (1 << (SI_SWINT1_INT1-1));
clear_c0_cause(0x100 << cpu_irq);
evpe(vpflags);
unmask_mips_mt_irq(irq);
return 0;
}
/*_____________________________________________________________________________
** function name: SLIC_reset
** descriptions:
** Reset or enable two SLIC devices
** parameters:
** reset: Identify the type of the operation to be performed
** global:
** None
** return:
** None
** call:
** None
** revision:
** 1.1 2008/09/26 14:30 Ian
**____________________________________________________________________________
*/
void SLIC_reset(int reset)
{
//printk("slic gpio:%d \n",SLIC1_GPIO);
//VPint(CR_GPIO_CTRL) |= (1<<((SLIC1_GPIO)*2));
if (SLIC1_GPIO <= 15)
{
VPint(CR_GPIO_CTRL) |= (1<<((SLIC1_GPIO*2)));
VPint(CR_GPIO_ODRAIN) |= (1<<(SLIC1_GPIO));
}
else
{
VPint(CR_GPIO_CTRL1) |= (1<<(((SLIC1_GPIO-16)*2)));
VPint(CR_GPIO_ODRAIN) |= (1<<(SLIC1_GPIO));
}
//printk("slic gpio:%d \n",SLIC2_GPIO);
// VPint(CR_GPIO_CTRL) |= (1<<((SLIC2_GPIO)*2));
// VPint(CR_GPIO_ODRAIN) |= (1<<(SLIC2_GPIO));
if (reset == RESET){
/**(volatile unsigned int*)0xAFF01404 &= ~RDGR_SLIC_SW_RST_L;**/
/*#warning "Must be Implement"*/
VPint(CR_GPIO_DATA) &= ~(1<<(SLIC1_GPIO));
//VPint(CR_GPIO_DATA) &= ~(1<<(SLIC2_GPIO));
}
else{
/**(volatile unsigned int*)0xAFF01404 |= RDGR_SLIC_SW_RST_L;**/
/*#warning "Must be Implement"*/
VPint(CR_GPIO_DATA) |= (1<<(SLIC1_GPIO));
//VPint(CR_GPIO_DATA) |= (1<<(SLIC2_GPIO));
}
}
int
uphy_init(void)
{
u32 i, reg_val, check_val, num_port_u2, num_port_u3;
if (atomic_inc_return(&uphy_init_instance) != 1)
return 0;
/* patch TxDetRx Timing for E1, from DR 20160421, Biker_20160516 */
reg_val = uphy_read32(ADDR_SIFSLV_PHYD_B2_BASE + 0x28);
reg_val &= ~(0x1ff << 9);
reg_val |= (0x010 << 9);
uphy_write32(ADDR_SIFSLV_PHYD_B2_BASE + 0x28, reg_val);
reg_val = uphy_read32(ADDR_SIFSLV_PHYD_B2_BASE + 0x2c);
reg_val &= ~0x1ff;
reg_val |= 0x010;
uphy_write32(ADDR_SIFSLV_PHYD_B2_BASE + 0x2c, reg_val);
/* patch LFPS Filter Threshold for E1, from DR 20160421, Biker_20160516 */
reg_val = uphy_read32(ADDR_SIFSLV_PHYD_BASE + 0x0c);
reg_val &= ~(0x3f << 16);
reg_val |= (0x34 << 16);
uphy_write32(ADDR_SIFSLV_PHYD_BASE + 0x0c, reg_val);
/* configure for XTAL 25MHz */
if (VPint(CR_AHB_HWCONF) & 0x01) {
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x1c, 0x18);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x1d, 0x18);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x1f, 0x18);
uphy_write32(ADDR_SIFSLV_PHYA_DA_BASE + 0x24, 0x18000000);
uphy_write32(ADDR_SIFSLV_PHYA_DA_BASE + 0x28, 0x18000000);
uphy_write32(ADDR_SIFSLV_PHYA_DA_BASE + 0x30, 0x18000000);
uphy_write32(ADDR_SIFSLV_PHYA_DA_BASE + 0x38, 0x004a004a);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x3e, 0x4a);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x3f, 0x0);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x42, 0x48);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x43, 0x0);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x44, 0x48);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x45, 0x0);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x48, 0x48);
uphy_write8(ADDR_SIFSLV_PHYA_DA_BASE + 0x49, 0x0);
uphy_write8(ADDR_SIFSLV_PHYA_BASE + 0x24, 0x90);
uphy_write8(ADDR_SIFSLV_PHYA_BASE + 0x25, 0x1);
uphy_write32(ADDR_SIFSLV_PHYA_BASE + 0x10, 0x1c000000);
uphy_write8(ADDR_SIFSLV_PHYA_BASE + 0x0b, 0xe);
}
reg_val = uphy_read32(REG_SSUSB_IP_CAP);
num_port_u3 = SSUSB_U3_PORT_NUM(reg_val);
num_port_u2 = SSUSB_U2_PORT_NUM(reg_val);
if (isEN7513 || isEN7513G) {
printk(KERN_INFO "%s USB PHY config\n", "EN7513 (BGA)");
uphy_write32(ADDR_U2_PHY_P0_BASE + 0x1c, 0xC0240008); /* enable port 0 */
uphy_write32(ADDR_U2_PHY_P1_BASE + 0x1c, 0xC0240000); /* enable port 1 */
} else if (isEN7512) {
printk(KERN_INFO "%s USB PHY config\n", "EN7512 (QFP)");
uphy_write32(ADDR_U2_PHY_P0_BASE + 0x1c, 0xC0241580); /* disable port 0 */
uphy_write32(ADDR_U2_PHY_P1_BASE + 0x1c, 0xC0240000); /* enable port 1 */
}
/* calibrate UPHY */
u2_slew_rate_calibration(0, ADDR_U2_PHY_P0_BASE);
u2_slew_rate_calibration(1, ADDR_U2_PHY_P1_BASE);
/* soft reset xHCI HC */
reg_val = uphy_read32(REG_SSUSB_IP_PW_CTRL0);
uphy_write32(REG_SSUSB_IP_PW_CTRL0, (reg_val | (SSUSB_IP_SW_RST)));
uphy_write32(REG_SSUSB_IP_PW_CTRL0, (reg_val & (~SSUSB_IP_SW_RST)));
/* enable xHCI HC power */
reg_val = uphy_read32(REG_SSUSB_IP_PW_CTRL1);
reg_val &= ~SSUSB_IP_PDN;
uphy_write32(REG_SSUSB_IP_PW_CTRL1, reg_val);
/* enable target USB3 ports */
for (i = 0; i < num_port_u3; i++) {
reg_val = uphy_read32(REG_SSUSB_U3_CTRL(i));
reg_val &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
uphy_write32(REG_SSUSB_U3_CTRL(i), reg_val);
}
/* enable target USB2 ports */
for (i = 0; i < num_port_u2; i++) {
reg_val = uphy_read32(REG_SSUSB_U2_CTRL(i));
reg_val &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
uphy_write32(REG_SSUSB_U2_CTRL(i), reg_val);
}
/* wait for clocks to be stable */
check_val = SSUSB_STS1_SYSPLL_STABLE |
SSUSB_STS1_REF_RST |
SSUSB_STS1_SYS125_RST |
SSUSB_STS1_XHCI_RST;
if (num_port_u3 > 0)
check_val |= SSUSB_STS1_U3_MAC_RST;
for (i = 0; i < 10; i++) {
msleep(50);
reg_val = uphy_read32(REG_SSUSB_IP_PW_STS1);
if ((reg_val & check_val) == check_val)
return 0;
}
printk(KERN_ERR "xhci clocks are not stable (IP_PW_STS1: 0x%x)\n", reg_val);
return -ENODEV;
}
static __init int tc3162_pci_init(void)
{
int pci_bios;
unsigned long x;
if(isRT63365)
return -1;
#ifndef CONFIG_MIPS_TC3262
pci_bios = VPint(CR_AHB_HWCONF) & (1<<8);
printk(KERN_INFO "tc3162: system has %sPCI BIOS\n",
pci_bios ? "" : "no ");
if (pci_bios == 0)
return -1;
#endif
VPint(CR_AHB_PCIC) &= ~(1<<31);
mdelay(100);
VPint(CR_AHB_PCIC) |= (1<<31);
mdelay(300);
/* PCI memory byte swap enable */
/*
VPint(CR_AHB_PCIC) |= (1<<24) | (1<<25);
*/
#ifdef CONFIG_MIPS_TC3262
/*read pci enable bit from PCI bridge command window to check pci support.
shnwind*/
VPint(PCI_COMMAND_WINDOW) = (1<<31);
pci_bios = VPint(PCI_COMMAND_WINDOW);
printk(KERN_INFO "system has %sPCI BIOS\n",pci_bios ? "" : "no ");
if (pci_bios == 0){
return -1;
}
#endif
/* Set I/O resource limits. */
ioport_resource.end = 0x1fffffff;
iomem_resource.end = 0xffffffff;
if(isRT63165)
{
/* rt63165's PCI bridge has additional config registers
* which can be direct-accessed, such as the first 3
* registers shown below
*/
//Disable PCI IO SWAP.
x = VPint(0xbfb000ec);
x &= ~(1<<9);
VPint(0xbfb000ec) = x;
/* configure USB Host Control Register to
do byte swaping in HW --Trey */
VPint(0xbfb000a8) = 0x00000060;
mdelay(10);
/* set space of PCI base address
up to 256M --Trey*/
VPint(0xbfb80010) = 0x0fff0001;
/* configure PCIArbitor Control Register to
set priority scheme --Trey*/
VPint(0xbfb80080) = 0x00000079;
//set base address of PCI
VPint(0xbfb80cf8) = 0x80000410;
VPint(0xbfb80cfc) = 0x00000000;
//enable PCI's master, memory functions
VPint(0xbfb80cf8) = 0x80000404;
VPint(0xbfb80cfc) = 0xa4800016;
//set PCI's latency-timer, cache-line-size
VPint(0xbfb80cf8) = 0x8000040c;
VPint(0xbfb80cfc) = 0x00002008;
}
register_pci_controller(&tc3162_controller);
return 0;
}
static void hw_reset(void)
{
#ifdef CONFIG_TC3162_ADSL
/* stop adsl */
if (adsl_dev_ops)
adsl_dev_ops->set(ADSL_SET_DMT_CLOSE, NULL, NULL);
#endif
/* stop each module dma task */
VPint(CR_INTC_IMR) = 0x0;
VPint(CR_TIMER_CTL) = 0x0;
/* stop mac dma */
#ifndef CONFIG_MIPS_TC3262
VPint(CR_MAC_MACCR) = 0;
#endif
/* stop atm sar dma */
TSARM_GFR &= ~((1 << 1) | (1 << 0));
/* reset USB */
/* reset USB DMA */
VPint(CR_USB_SYS_CTRL_REG) |= (1 << 31);
/* reset USB SIE */
VPint(CR_USB_DEV_CTRL_REG) |= (1 << 30);
mdelay(5);
/* restore USB SIE */
VPint(CR_USB_DEV_CTRL_REG) &= ~(1 << 30);
mdelay(5);
VPint(CR_USB_SYS_CTRL_REG) &= ~(1 << 31);
#ifdef CONFIG_MIPS_TC3162U
/*stop pcie*/
VPint(CR_AHB_PCIC) &= 0x9fffffff;
/*reset usb 2.0 device*/
/*stop interrupt*/
VPint(CR_USB20_INTR_ENABLE_REG) = 0x0;
/*do usb reset*/
VPint(CR_USB20_SYS_CTRL_REG) |= (1 << 31);
mdelay(1);
VPint(CR_USB20_SYS_CTRL_REG) &= ~(1 << 31);
/*sw disconnect*/
VPint(CR_USB20_DEV_CTRL_REG) |= (1 << 31);
#endif
/* watchdog reset */
//#ifdef CONFIG_MIPS_TC3262
timerSet(5, 10 * TIMERTICKS_10MS, ENABLE, TIMER_TOGGLEMODE, TIMER_HALTDISABLE);
timer_WatchDogConfigure(ENABLE, ENABLE);
while (1);
//#endif
}
__IMEM static inline void unmask_mips_irq(unsigned int irq)
{
#ifdef CONFIG_MIPS_TC3262
unsigned long flags;
int cpu = smp_processor_id();
spin_lock_irqsave(&tc3162_irq_lock, flags);
#ifdef CONFIG_MIPS_MT_SMTC
if (cpu_data[cpu].vpe_id != 0) {
#else
if (cpu != 0) {
#endif
if (irq == SI_TIMER_INT)
irq = SI_TIMER1_INT;
}
if (irq <= 32)
VPint(CR_INTC_IMR) |= (1 << (irq-1));
else
VPint(CR_INTC_IMR_1) |= (1 << (irq-33));
spin_unlock_irqrestore(&tc3162_irq_lock, flags);
#else
VPint(CR_INTC_IMR) |= (1 << irq);
#endif
}
__IMEM static inline void mask_mips_irq(unsigned int irq)
{
#ifdef CONFIG_MIPS_TC3262
unsigned long flags;
int cpu = smp_processor_id();
spin_lock_irqsave(&tc3162_irq_lock, flags);
#ifdef CONFIG_MIPS_MT_SMTC
if (cpu_data[cpu].vpe_id != 0) {
#else
if (cpu != 0) {
#endif
if (irq == SI_TIMER_INT)
irq = SI_TIMER1_INT;
}
if (irq <= 32)
VPint(CR_INTC_IMR) &= ~(1 << (irq-1));
else
VPint(CR_INTC_IMR_1) &= ~(1 << (irq-33));
spin_unlock_irqrestore(&tc3162_irq_lock, flags);
#else
VPint(CR_INTC_IMR) &= ~(1 << irq);
#endif
}
void tc3162_enable_irq(unsigned int irq)
{
#ifdef CONFIG_MIPS_TC3262
unsigned long flags;
spin_lock_irqsave(&tc3162_irq_lock, flags);
if (irq <= 32)
VPint(CR_INTC_IMR) |= (1 << (irq-1));
else
VPint(CR_INTC_IMR_1) |= (1 << (irq-33));
spin_unlock_irqrestore(&tc3162_irq_lock, flags);
#else
VPint(CR_INTC_IMR) |= (1 << irq);
#endif
}
