// pProgress = Bar_ProgressStart( stdout, Aig_ManCoNum(p) );
Aig_ManForEachCo( p, pObj, i )
{
// Bar_ProgressUpdate( pProgress, i, NULL );
// get old supports
vSup = Vec_VecEntryInt( vSupps, i );
if ( Vec_IntSize(vSup) < 2 )
continue;
// compute new supports
CountOver = CountQuant = 0;
vSupNew = Vec_IntDup( vSup );
// go through the nodes where the first var appears
Aig_ManForEachCo( p, pObj, k )
// iVar = Vec_IntEntry( vSup, 0 );
// vSupIn = Vec_VecEntry( vSuppsIn, iVar );
// Vec_IntForEachEntry( vSupIn, Entry, k )
{
// pObj = Aig_ManObj( p, Entry );
// get support of this output
// vSup2 = (Vec_Int_t *)pObj->pNext;
vSup2 = Vec_VecEntryInt( vSupps, k );
// count the number of common vars
nCommon = Vec_IntTwoCountCommon(vSup, vSup2);
if ( nCommon < 2 )
continue;
if ( nCommon > nComLim )
{
vSupNew = Vec_IntTwoMerge( vTemp = vSupNew, vSup2 );
Vec_IntFree( vTemp );
CountOver++;
}
else
CountQuant++;
}
/**Function*************************************************************
Synopsis [Duplicates the AIG manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Aig_Man_t * Aig_ManDup( Aig_Man_t * p, int fOrdered )
{
Aig_Man_t * pNew;
Aig_Obj_t * pObj;
int i;
// create the new manager
pNew = Aig_ManStart( Aig_ManObjNumMax(p) );
pNew->pName = Aig_UtilStrsav( p->pName );
pNew->nRegs = p->nRegs;
pNew->nAsserts = p->nAsserts;
if ( p->vFlopNums )
pNew->vFlopNums = Vec_IntDup( p->vFlopNums );
// create the PIs
Aig_ManCleanData( p );
Aig_ManConst1(p)->pData = Aig_ManConst1(pNew);
Aig_ManForEachPi( p, pObj, i )
pObj->pData = Aig_ObjCreatePi(pNew);
// duplicate internal nodes
if ( fOrdered )
{
Aig_ManForEachObj( p, pObj, i )
if ( Aig_ObjIsBuf(pObj) )
pObj->pData = Aig_ObjChild0Copy(pObj);
else if ( Aig_ObjIsNode(pObj) )
pObj->pData = Aig_And( pNew, Aig_ObjChild0Copy(pObj), Aig_ObjChild1Copy(pObj) );
}
else
{
/**Function*************************************************************
Synopsis [Computes initial values of the new latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Abc_NtkRetimeInitialValues( Abc_Ntk_t * pNtkCone, Vec_Int_t * vValues, int fVerbose )
{
Vec_Int_t * vSolution;
Abc_Ntk_t * pNtkMiter, * pNtkLogic;
int RetValue;
abctime clk;
if ( pNtkCone == NULL )
return Vec_IntDup( vValues );
// convert the target network to AIG
pNtkLogic = Abc_NtkDup( pNtkCone );
Abc_NtkToAig( pNtkLogic );
// get the miter
pNtkMiter = Abc_NtkCreateTarget( pNtkLogic, pNtkLogic->vCos, vValues );
if ( fVerbose )
printf( "The miter for initial state computation has %d AIG nodes. ", Abc_NtkNodeNum(pNtkMiter) );
// solve the miter
clk = Abc_Clock();
RetValue = Abc_NtkMiterSat( pNtkMiter, (ABC_INT64_T)500000, (ABC_INT64_T)50000000, 0, NULL, NULL );
if ( fVerbose )
{ ABC_PRT( "SAT solving time", Abc_Clock() - clk ); }
// analyze the result
if ( RetValue == 1 )
printf( "Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.\n" );
else if ( RetValue == -1 )
printf( "Abc_NtkRetimeInitialValues(): The SAT problem timed out. DC latch values are used.\n" );
else if ( !Abc_NtkRetimeVerifyModel( pNtkCone, vValues, pNtkMiter->pModel ) )
printf( "Abc_NtkRetimeInitialValues(): The computed counter-example is incorrect.\n" );
// set the values of the latches
vSolution = RetValue? NULL : Vec_IntAllocArray( pNtkMiter->pModel, Abc_NtkPiNum(pNtkLogic) );
pNtkMiter->pModel = NULL;
Abc_NtkDelete( pNtkMiter );
Abc_NtkDelete( pNtkLogic );
return vSolution;
}
int Gia_Iso3Unique( Vec_Int_t * vSign )
{
int nUnique;
Vec_Int_t * vCopy = Vec_IntDup( vSign );
Vec_IntUniqify( vCopy );
nUnique = Vec_IntSize(vCopy);
Vec_IntFree( vCopy );
return nUnique;
}