SC_LibForEachWireLoadSel( p, pWLS, i )
{
Vec_StrPutS( vOut, pWLS->pName );
Vec_StrPutI( vOut, Vec_FltSize(pWLS->vAreaFrom) );
for ( j = 0; j < Vec_FltSize(pWLS->vAreaFrom); j++)
{
Vec_StrPutF( vOut, Vec_FltEntry(pWLS->vAreaFrom, j) );
Vec_StrPutF( vOut, Vec_FltEntry(pWLS->vAreaTo, j) );
Vec_StrPutS( vOut, (char *)Vec_PtrEntry(pWLS->vWireLoadModel, j) );
}
}
SC_CellForEachPinOut( pCell, pPin, j )
{
SC_Timings * pRTime;
word uWord;
assert(pPin->dir == sc_dir_Output);
Vec_StrPutS( vOut, pPin->pName );
Vec_StrPutF( vOut, pPin->max_out_cap );
Vec_StrPutF( vOut, pPin->max_out_slew );
// write function
if ( pPin->func_text == NULL )
{
// formula is not given - write empty string
Vec_StrPutS( vOut, "" );
// write truth table
assert( Vec_WrdSize(pPin->vFunc) == Abc_Truth6WordNum(pCell->n_inputs) );
Vec_StrPutI( vOut, pCell->n_inputs );
Vec_WrdForEachEntry( pPin->vFunc, uWord, k ) // -- 'size = 1u << (n_vars - 6)'
Vec_StrPutW( vOut, uWord ); // -- 64-bit number, written uncompressed (low-byte first)
}
else // formula is given
Vec_StrPutS( vOut, pPin->func_text );
// Write 'rtiming': (pin-to-pin timing tables for this particular output)
assert( Vec_PtrSize(pPin->vRTimings) == pCell->n_inputs );
SC_PinForEachRTiming( pPin, pRTime, k )
{
Vec_StrPutS( vOut, pRTime->pName );
Vec_StrPutI( vOut, Vec_PtrSize(pRTime->vTimings) );
// -- NOTE! After post-processing, the size of the 'rtiming[k]' vector is either
// 0 or 1 (in static timing, we have merged all tables to get the worst case).
// The case with size 0 should only occur for multi-output gates.
if ( Vec_PtrSize(pRTime->vTimings) == 1 )
{
SC_Timing * pTime = (SC_Timing *)Vec_PtrEntry( pRTime->vTimings, 0 );
// -- NOTE! We don't need to save 'related_pin' string because we have sorted
// the elements on input pins.
Vec_StrPutI( vOut, (int)pTime->tsense);
Abc_SclWriteSurface( vOut, pTime->pCellRise );
Abc_SclWriteSurface( vOut, pTime->pCellFall );
Abc_SclWriteSurface( vOut, pTime->pRiseTrans );
Abc_SclWriteSurface( vOut, pTime->pFallTrans );
}
else
assert( Vec_PtrSize(pRTime->vTimings) == 0 );
}
SC_LibForEachCell( p, pCell, i )
{
if ( pCell->seq || pCell->unsupp )
continue;
Vec_StrPutS( vOut, pCell->pName );
Vec_StrPutF( vOut, pCell->area );
Vec_StrPutI( vOut, pCell->drive_strength );
// Write 'pins': (sorted at this point; first inputs, then outputs)
Vec_StrPutI( vOut, pCell->n_inputs);
Vec_StrPutI( vOut, pCell->n_outputs);
SC_CellForEachPinIn( pCell, pPin, j )
{
assert(pPin->dir == sc_dir_Input);
Vec_StrPutS( vOut, pPin->pName );
Vec_StrPutF( vOut, pPin->rise_cap );
Vec_StrPutF( vOut, pPin->fall_cap );
}
/**Function*************************************************************
Synopsis [Writing library into file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
static void Abc_SclWriteSurface( Vec_Str_t * vOut, SC_Surface * p )
{
Vec_Flt_t * vVec;
float Entry;
int i, k;
Vec_StrPutI( vOut, Vec_FltSize(p->vIndex0) );
Vec_FltForEachEntry( p->vIndex0, Entry, i )
Vec_StrPutF( vOut, Entry );
Vec_StrPutI( vOut, Vec_FltSize(p->vIndex1) );
Vec_FltForEachEntry( p->vIndex1, Entry, i )
Vec_StrPutF( vOut, Entry );
Vec_PtrForEachEntry( Vec_Flt_t *, p->vData, vVec, i )
Vec_FltForEachEntry( vVec, Entry, k )
Vec_StrPutF( vOut, Entry );
for ( i = 0; i < 3; i++ )
Vec_StrPutF( vOut, p->approx[0][i] );
for ( i = 0; i < 4; i++ )
Vec_StrPutF( vOut, p->approx[1][i] );
for ( i = 0; i < 6; i++ )
Vec_StrPutF( vOut, p->approx[2][i] );
}
static void Abc_SclWriteLibrary( Vec_Str_t * vOut, SC_Lib * p )
{
SC_WireLoad * pWL;
SC_WireLoadSel * pWLS;
SC_Cell * pCell;
SC_Pin * pPin;
int n_valid_cells;
int i, j, k;
Vec_StrPutI( vOut, ABC_SCL_CUR_VERSION );
// Write non-composite fields:
Vec_StrPutS( vOut, p->pName );
Vec_StrPutS( vOut, p->default_wire_load );
Vec_StrPutS( vOut, p->default_wire_load_sel );
Vec_StrPutF( vOut, p->default_max_out_slew );
assert( p->unit_time >= 0 );
assert( p->unit_cap_snd >= 0 );
Vec_StrPutI( vOut, p->unit_time );
Vec_StrPutF( vOut, p->unit_cap_fst );
Vec_StrPutI( vOut, p->unit_cap_snd );
// Write 'wire_load' vector:
Vec_StrPutI( vOut, Vec_PtrSize(p->vWireLoads) );
SC_LibForEachWireLoad( p, pWL, i )
{
Vec_StrPutS( vOut, pWL->pName );
Vec_StrPutF( vOut, pWL->res );
Vec_StrPutF( vOut, pWL->cap );
Vec_StrPutI( vOut, Vec_IntSize(pWL->vFanout) );
for ( j = 0; j < Vec_IntSize(pWL->vFanout); j++ )
{
Vec_StrPutI( vOut, Vec_IntEntry(pWL->vFanout, j) );
Vec_StrPutF( vOut, Vec_FltEntry(pWL->vLen, j) );
}
}
