QString comp_1bit::verilogCode( int )
{
QString l="";
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString X = Ports.at(0)->Connection->Name;
QString Y = Ports.at(1)->Connection->Name;
QString L = Ports.at(2)->Connection->Name;
QString G = Ports.at(3)->Connection->Name;
QString E = Ports.at(4)->Connection->Name;
QString LR = "L_reg" + Name + L;
QString GR = "G_reg" + Name + G;
QString ER = "E_reg" + Name + E;
l = "\n // "+Name+" 1bit comparator\n"+
" assign "+L+" = "+LR+";\n"+
" reg "+LR+" = 0;\n"+
" assign "+G+" = "+GR+";\n"+
" reg "+GR+" = 0;\n"+
" assign "+E+" = "+ER+";\n"+
" reg "+ER+" = 0;\n"+
" always @ ("+X+" or "+Y+")\n"+
" begin\n"+
" "+LR+" <="+td+" (~"+X+") && "+Y+";\n"+
" "+GR+" <="+td+" "+X+" && (~"+Y+");\n"+
" "+ER+" <="+td+" ~("+X+" ^ "+Y+");\n"+
" end\n";
return l;
}
// -------------------------------------------------------
QString JK_FlipFlop::verilogCode(int NumPorts)
{
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
if(!td.isEmpty()) t = " " + td + ";\n";
}
QString l = "";
QString s = Ports.at(5)->Connection->Name;
QString r = Ports.at(6)->Connection->Name;
QString j = Ports.at(0)->Connection->Name;
QString k = Ports.at(1)->Connection->Name;
QString q = Ports.at(2)->Connection->Name;
QString b = Ports.at(3)->Connection->Name;
QString c = Ports.at(4)->Connection->Name;
QString v = "net_reg" + Name + q;
l = "\n // " + Name + " JK-flipflop\n" +
" assign " + q + " = " + v + ";\n" +
" assign " + b + " = ~" + q + ";\n" +
" reg " + v + " = 0;\n" +
" always @ (" + c + " or " + r + " or " + s + ") begin\n" + t +
" if (" + r + ") " + v + " <= 0;\n" +
" else if (" + s + ") " + v + " <= 1;\n" +
" else if (" + c + ")\n" +
" " + v + " <= (" + j + " && ~" + q + ") || (~" +
k + " && " + q + ");\n" +
" end\n\n";
return l;
}
QString mux2to1::verilogCode( int )
{
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name))
return td; // Time does not have VHDL format.
td += " ";
QString l = "";
QString En = Ports.at(0)->Connection->Name;
QString A = Ports.at(1)->Connection->Name;
QString D0 = Ports.at(2)->Connection->Name;
QString D1 = Ports.at(3)->Connection->Name;
QString y = Ports.at(4)->Connection->Name;
QString v = "net_reg" + Name + y;
l = "\n // " + Name + " 2to1 mux\n" +
" assign " + y + " = " + v + ";\n" +
" reg " + v + " = 0;\n" +
" always @ (" + En + " or " + A + " or "
+ D0 + " or " + D1 + ")\n" +
" " + v + " <=" + td + "(" + D1 + " && " + A + ")" + " || " +
"(" + D0 + " && (~" + A + "));\n" ;
return l;
}
QString andor4x2::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString a11 = Ports.at(0)->Connection->Name;
QString a12 = Ports.at(1)->Connection->Name;
QString a21 = Ports.at(2)->Connection->Name;
QString a22 = Ports.at(3)->Connection->Name;
QString a31 = Ports.at(4)->Connection->Name;
QString a32 = Ports.at(5)->Connection->Name;
QString a41 = Ports.at(6)->Connection->Name;
QString a42 = Ports.at(7)->Connection->Name;
QString y = Ports.at(8)->Connection->Name;
QString v = "net_reg" + Name + y;
l = "\n // " + Name + " 4x2 andor\n" +
" assign " + y + " = " + v + ";\n" +
" reg " + v + " = 0;\n" +
" always @ (" + a11 + " or " + a12 + " or "
+ a21 + " or " + a22 + " or "
+ a31 + " or " + a32 + " or "
+ a41 + " or " + a42 + ")\n " +
" " + v + " <=" + td + " (" + a11 + " && " + a12 + ")" + " || " +
"(" + a21 + " && " + a22 + ")" + " || " +
"(" + a31 + " && " + a32 + ")" + " || " +
"(" + a41 + " && " + a42 + ")" + ";\n" ;
return l;
}
QString fa1b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString A = Ports.at(0)->Connection->Name;
QString B = Ports.at(1)->Connection->Name;
QString CI = Ports.at(2)->Connection->Name;
QString CO = Ports.at(3)->Connection->Name;
QString S = Ports.at(4)->Connection->Name;
QString COR = "CO_reg" + Name + CO;
QString SR = "S_reg" + Name + S;
l = "\n // " + Name + " 1bit fulladder\n" +
" assign " + CO + " = " + COR + ";\n" +
" reg " + COR + " = 0;\n" +
" assign " + S + " = " + SR + ";\n" +
" reg " + SR + " = 0;\n" +
" always @ ("+ A + " or " + B + " or " + CI + ")\n" +
" begin\n" +
" " + COR + " <=" + td + " (" + A + " && " + B + ") || " + CI + " && " + "(" + A + " ^ " + B + ");\n" +
" " + SR + " <=" + td + " (" + CI + " ^ " + A + " ^ " + B + ");\n" +
" end\n";
return l;
}
QString hpribin4bit::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString A = Ports.at(0)->Connection->Name;
QString B = Ports.at(1)->Connection->Name;
QString C = Ports.at(2)->Connection->Name;
QString D = Ports.at(3)->Connection->Name;
QString V = Ports.at(4)->Connection->Name;
QString Y = Ports.at(5)->Connection->Name;
QString X = Ports.at(6)->Connection->Name;
QString VR = "V_reg" + Name + V;
QString YR = "Y_reg" + Name + Y;
QString XR = "X_reg" + Name + X;
l = "\n // "+Name+" 4bit hpribin\n"+
" assign "+V+" = "+VR+";\n"+
" reg "+VR+" = 0;\n"+
" assign "+Y+" = "+YR+";\n"+
" reg "+YR+" = 0;\n"+
" assign "+X+" = "+XR+";\n"+
" reg "+XR+" = 0;\n"+
" always @ ("+A+" or "+B+" or "+C+" or "+D+")\n"+
" begin\n" +
" " +XR+" <="+td+" "+D+" || "+C+";\n"+
" " +YR+" <="+td+" "+D+" || ((~"+C+") && "+B+");\n" +
" " +VR+" <="+td+" "+D+" || "+C+" || "+B+" || "+A+";\n"+
" end\n";
return l;
}
QString gatedDlatch::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString D = Ports.at(0)->Connection->Name;
QString C = Ports.at(1)->Connection->Name;
QString QB = Ports.at(2)->Connection->Name;
QString Q = Ports.at(3)->Connection->Name;
QString QR = "Q_reg" + Name + Q;
QString QBR = "QB_reg" + Name + QB;
l = "\n // "+Name+" gated d latch\n"+
" assign "+Q+" = "+QR+";\n"+
" reg "+QR+" = 0;\n"+
" assign "+QB+" = "+QBR+";\n"+
" reg "+QBR+" = 0;\n"+
" always @ ("+D+" or "+C+")\n"+
" begin\n"+
" if ("+C+" == 1)\n"+
" begin\n"+
" " +QR+" <="+td+" "+D+";\n"+
" " +QBR+" <="+td+" ~"+D+";\n" +
" end\n"+
" end\n";
return l;
}
QString mux4to1::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString En = Ports.at(0)->Connection->Name;
QString A = Ports.at(1)->Connection->Name;
QString B = Ports.at(2)->Connection->Name;
QString D0 = Ports.at(3)->Connection->Name;
QString D1 = Ports.at(4)->Connection->Name;
QString D2 = Ports.at(5)->Connection->Name;
QString D3 = Ports.at(6)->Connection->Name;
QString y = Ports.at(7)->Connection->Name;
QString v = "net_reg" + Name + y;
l = "\n // " + Name + " 4to1 mux\n" +
" assign " + y + " = " + v + ";\n" +
" reg " + v + " = 0;\n" +
" always @ (" + En + " or " + A + " or " + B + " or "
+ D0 + " or " + D1 + " or " + D2 + " or " + D0 + ")\n" +
" " + v + " <=" + td + " (" + D3 + " && " + B + " && " + A +")" + " ||\n" +
" (" + D2 + " && " + B + " && ~"+ A +")" + " ||\n" +
" (" + D1 + " && ~"+ B + " && " + A +")" + " ||\n" +
" (" + D0 + " && ~"+ B + " && ~"+ A +");\n";
return l;
}
QString comp_4bit::verilogCode( int )
{
QString l="";
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString X0 = Ports.at(0)->Connection->Name;
QString X1 = Ports.at(1)->Connection->Name;
QString X2 = Ports.at(2)->Connection->Name;
QString X3 = Ports.at(3)->Connection->Name;
QString Y0 = Ports.at(4)->Connection->Name;
QString Y1 = Ports.at(5)->Connection->Name;
QString Y2 = Ports.at(6)->Connection->Name;
QString Y3 = Ports.at(7)->Connection->Name;
QString L = Ports.at(8)->Connection->Name;
QString G = Ports.at(9)->Connection->Name;
QString E = Ports.at(10)->Connection->Name;
QString LR = "L_reg" + Name + L;
QString GR = "G_reg" + Name + G;
QString ER = "E_reg" + Name + E;
l = "\n // "+Name+" 4bit comparator\n"+
" assign "+L+" = "+LR+";\n"+
" reg "+LR+" = 0;\n"+
" assign "+G+" = "+GR+";\n"+
" reg "+GR+" = 0;\n"+
" assign "+E+" = "+ER+";\n"+
" reg "+ER+" = 0;\n"+
" reg P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11;\n"+
" always @ ("+X0+" or "+X1+" or "+X2+" or "+X3+" or "+Y0+" or "+Y1+" or "+Y2+" or "+Y3+")\n"+
" begin\n"+
" P0 = ~("+X0+" ^ "+Y0+");\n"+
" P1 = ~("+X1+" ^ "+Y1+");\n"+
" P2 = ~("+X2+" ^ "+Y2+");\n"+
" P3 = ~("+X3+" ^ "+Y3+");\n"+
" P4 = (~"+X0+") && "+Y0+";\n"+
" P5 = (~"+X1+") && "+Y1+";\n"+
" P6 = (~"+X2+") && "+Y2+";\n"+
" P7 = (~"+X3+") && "+Y3+";\n"+
" P8 = "+X0+" && (~"+Y0+");\n"+
" P9 = "+X1+" && (~"+Y1+");\n"+
" P10 = "+X2+" && (~"+Y2+");\n"+
" P11 = "+X3+" && (~"+Y3+");\n"+
" "+LR+" <="+td+" P7 || (P3 && P6) || (P3 && P2 && P5) || (P3 && P2 && P1 && P4)"+";\n"+
" "+GR+" <="+td+" P11 || (P3 && P10) || (P3 && P2 && P9) || (P3 && P2 && P1 && P8)"+";\n"+
" "+ER+" <="+td+" P3 && P2 && P1 && P0"+";\n"+
" end\n";
return l;
}
// -------------------------------------------------------
QString Logical_Inv::verilogCode(int NumPorts)
{
bool synthesize = true;
Port *pp = Ports.first();
QString s ("");
if (synthesize) {
s = " assign";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name)) return td;
s += td;
}
s += " ";
s += pp->Connection->Name + " = "; // output port
pp = Ports.next();
s += "~" + pp->Connection->Name; // input port
s += ";\n";
}
else {
s = " not";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name))
return td; // time has not VHDL format
s += td;
}
s += " " + Name + " (" + pp->Connection->Name; // output port
pp = Ports.next();
s += ", " + pp->Connection->Name; // first input port
s += ");\n";
}
return s;
}
QString dff_SR::verilogCode( int )
{
QString td = Props.at(2)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString S = Ports.at(0)->Connection->Name;
QString D = Ports.at(1)->Connection->Name;
QString CLK = Ports.at(2)->Connection->Name;
QString R = Ports.at(3)->Connection->Name;
QString QB = Ports.at(4)->Connection->Name;
QString Q = Ports.at(5)->Connection->Name;
QString QR = "Q_reg" + Name + Q;
QString QBR = "QB_reg" + Name + QB;
QString ST = "Q_state" + Name;
l = "\n // "+Name+" d flip-flop with set and reset\n"+
" assign "+Q+" = "+QR+";\n"+
" reg "+QR+" = 0;\n"+
" assign "+QB+" = "+QBR+";\n"+
" reg "+QBR+" = 1;\n"+
" reg "+ST+" = 0;\n"+
" always @ (posedge "+CLK+")\n"+
" begin\n"+
" if ("+R+" == 1 && "+S+" == 1)\n"+
" begin\n"+
" "+ST+" = "+D+";\n"+
" "+QR+" <="+td+" "+ST+";\n"+
" "+QBR+" <="+td+" ~"+ST+";\n"+
" end\n"+
" end\n"+
" always @ ("+R+")\n"+
" begin\n"+
" if ("+R+" == 0) "+ST+" = 0;\n"+
" "+QR+" <="+td+" "+ST+";\n"+
" "+QBR+" <="+td+" ~"+ST+";\n"+
" end\n"+
" always @ ("+S+")\n"+
" begin if ("+S+" == 0) "+ST+" = 1;\n"+
" "+QR+" <="+td+" "+ST+";\n"+
" "+QBR+" <="+td+" ~"+ST+";\n"+
" end\n";
return l;
}
// -------------------------------------------------------
QString Digi_Source::verilogCode(int NumPorts)
{
QString s, t, n, r;
n = Ports.getFirst()->Connection->Name;
r = "net_src" + Name + n;
s = "\n // " + Name + " digital source\n";
s += " assign " + n + " = " + r + ";\n";
s += " reg " + r + ";\n";
int z = 0;
char State;
if(NumPorts <= 0) { // time table simulation ?
if(Props.at(1)->Value == "low")
State = '0';
else
State = '1';
s += " always begin\n";
t = Props.next()->Value.section(';',z,z).stripWhiteSpace();
while(!t.isEmpty()) {
if(!Verilog_Delay(t, Name))
return t; // time has not VHDL format
s += " " + r + " = " + State + ";\n";
s += " " + t + ";\n";
State ^= 1;
z++;
t = Props.current()->Value.section(';',z,z).stripWhiteSpace();
}
}
else { // truth table simulation
int Num = Props.getFirst()->Value.toInt() - 1;
s += " always begin\n";
s += " " + r + " = 0;\n";
s += " #"+ QString::number(1 << Num) + ";\n";
s += " " + r + " = !" + r + ";\n";
s += " #"+ QString::number(1 << Num) + ";\n";
}
s += " end\n";
return s;
}
// -------------------------------------------------------
QString RS_FlipFlop::verilogCode(int NumPorts)
{
QString t = "";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(0)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time has not VHDL format
t = td;
}
t += " ";
QString l = "";
QString s = Ports.at(1)->Connection->Name;
QString r = Ports.at(0)->Connection->Name;
QString q = Ports.at(2)->Connection->Name;
QString b = Ports.at(3)->Connection->Name;
l = "\n // " + Name + " RS-flipflop\n" +
" assign" + t + q + " = ~(" + r + " | " + b + ");\n" +
" assign" + t + b + " = ~(" + s + " | " + q + ");\n\n";
return l;
}
// -------------------------------------------------------
QString Logical_Buf::verilogCode(int NumPorts)
{
bool synthesize = true;
Port *pp = Ports.at(0);
QString s ("");
if (synthesize) {
s = " assign";
if(NumPorts <= 0) { // no truth table simulation ?
QString td = Props.at(1)->Value;
if(!Verilog_Delay(td, Name)) return td;
s += td;
}
s += " ";
s += pp->Connection->Name + " = "; // output port
pp = Ports.at(1);
s += pp->Connection->Name; // input port
s += ";\n";
}
return s;
}
QString fa2b::verilogCode( int )
{
QString td = Props.at(1)->Value; // delay time
if(!Verilog_Delay(td, Name)) return td; // time does not have VHDL format
QString l = "";
QString D = Ports.at(0)->Connection->Name;
QString C = Ports.at(1)->Connection->Name;
QString B = Ports.at(2)->Connection->Name;
QString A = Ports.at(3)->Connection->Name;
QString E = Ports.at(4)->Connection->Name;
QString CO = Ports.at(5)->Connection->Name;
QString S1 = Ports.at(6)->Connection->Name;
QString S0 = Ports.at(7)->Connection->Name;
QString COR = "CO_reg" + Name + CO;
QString S1R = "S1_reg" + Name + S1;
QString S0R = "S0_reg" + Name + S0;
l = "\n // "+Name+" 2bit fulladder\n"+
" assign "+CO+" = "+COR+";\n"+
" reg "+COR+" = 0;\n"+
" assign "+S1+" = "+S1R+";\n"+
" reg "+S1R+" = 0;\n"+
" assign "+S0+" = "+S0R+";\n"+
" reg "+S0R+" = 0;\n"+
" always @ ("+A+" or "+B+" or "+C+" or "+D+" or "+E+")\n"+
" begin\n" +
" " +COR+" <="+td+" ("+A+" && "+C+") || ("+A+" || "+C+") && ("+B+" && "+D+" || "+E+" && "+B+" || "+E+" && "+D+");\n"+
" " +S1R+" <="+td+" ("+B+" && "+D+" || "+E+" && "+B+" || "+E+" && "+D+") ^ ("+A+" ^ "+C+");\n" +
" " +S0R+" <="+td+" "+E+" ^ ("+B+" ^ "+D+");\n"+
" end\n";
return l;
}
