void snd_aw2_saa7146_pcm_init_capture(struct snd_aw2_saa7146 *chip,
int stream_number, unsigned long dma_addr,
unsigned long period_size,
unsigned long buffer_size)
{
unsigned long dw_page, dw_limit;
dw_page = (0L << 11);
dw_limit = snd_aw2_saa7146_get_limit(period_size);
dw_page |= (dw_limit << 4);
if (stream_number == 0) {
WRITEREG(dw_page, PageA1_in);
WRITEREG(dma_addr, BaseA1_in);
WRITEREG(dma_addr + buffer_size, ProtA1_in);
} else {
printk(KERN_ERR
"aw2: snd_aw2_saa7146_pcm_init_capture: "
"Substream number is not 0 -> not managed\n");
}
}
/*
On button click the corresponding led will blink thrice
*/
void blinkthrice(){
WRITEREG(PORTB, ~BV(lastLED)); /*Restrat the LED rotation from first LED*/
//PORTB = ~BV(lastLED);
delay(blinkDelay);
//PORTB = 0xFF;
WRITEREG(PORTB, 0xFF); /*Restrat the LED rotation from first LED*/
delay(blinkDelay);
}
void snd_aw2_saa7146_use_digital_input(struct snd_aw2_saa7146 *chip,
int use_digital)
{
if (use_digital)
WRITEREG(0x40, GPIO_CTRL);
else
WRITEREG(0x50, GPIO_CTRL);
}
/* chip-specific destructor */
int snd_aw2_saa7146_free(struct snd_aw2_saa7146 *chip)
{
/* disable all irqs */
WRITEREG(0, IER);
/* reset saa7146 */
WRITEREG((MRST_N << 16), MC1);
/* Unset base addr */
chip->base_addr = NULL;
return 0;
}
int snd_aw2_saa7146_free(struct snd_aw2_saa7146 *chip)
{
WRITEREG(0, IER);
WRITEREG((MRST_N << 16), MC1);
chip->base_addr = NULL;
return 0;
}
void snd_aw2_saa7146_use_digital_input(struct snd_aw2_saa7146 *chip,
int use_digital)
{
/* FIXME: switch between analog and digital input does not always work.
It can produce a kind of white noise. It seams that received data
are inverted sometime (endian inversion). Why ? I don't know, maybe
a problem of synchronization... However for the time being I have
not found the problem. Workaround: switch again (and again) between
digital and analog input until it works. */
if (use_digital)
WRITEREG(0x40, GPIO_CTRL);
else
WRITEREG(0x50, GPIO_CTRL);
}
void onButtonPress(){
cli(); /*This takes care of the timer interrupts which was causing issues*/
/*Setting the lastLED to be lit based on the pin selection. While rotating the last LED to light up would be the switch that was pressed*/
if(~swPressed & 0x01)
lastLED = 0;
else if(~swPressed & 0x02)
lastLED = 1;
else if(~swPressed & 0x04)
lastLED = 2;
else if(~swPressed & 0x08)
lastLED = 3;
else if(~swPressed & 0x10)
lastLED = 4;
else if(~swPressed & 0x20)
lastLED = 5;
else if(~swPressed & 0x40)
lastLED = 6;
else if(~swPressed & 0x80)
lastLED = 7;
pinBit = 0;
//PORTB = ~_BV(lastLED); /*.... Start LED Toggle from the first bit ie Bit 0*/
blinkthrice();
WRITEREG(PORTB,0xFF);
//PORTB = 0xFF;
swPressed = 0; /*A poor implementation */
sei();
}
void snd_aw2_saa7146_pcm_trigger_start_capture(struct snd_aw2_saa7146 *chip,
int stream_number)
{
/* In aw8 driver, dma transfert is always active. It is
started and stopped in a larger "space" */
if (stream_number == 0)
WRITEREG((TR_E_A1_IN << 16) | TR_E_A1_IN, MC1);
}
void snd_aw2_saa7146_pcm_init_capture(struct snd_aw2_saa7146 *chip,
int stream_number, unsigned long dma_addr,
unsigned long period_size,
unsigned long buffer_size)
{
unsigned long dw_page, dw_limit;
/* Configure DMA for substream
Configuration informations: ALSA has allocated continuous memory
pages. So we don't need to use MMU of saa7146.
*/
/* No MMU -> nothing to do with PageA1, we only configure the limit of
PageAx_out register */
/* Disable MMU */
dw_page = (0L << 11);
/* Configure Limit for DMA access.
The limit register defines an address limit, which generates
an interrupt if passed by the actual PCI address pointer.
'0001' means an interrupt will be generated if the lower
6 bits (64 bytes) of the PCI address are zero. '0010'
defines a limit of 128 bytes, '0011' one of 256 bytes, and
so on up to 1 Mbyte defined by '1111'. This interrupt range
can be calculated as follows:
Range = 2^(5 + Limit) bytes.
*/
dw_limit = snd_aw2_saa7146_get_limit(period_size);
dw_page |= (dw_limit << 4);
if (stream_number == 0) {
WRITEREG(dw_page, PageA1_in);
/* Base address for DMA transfert. */
/* This address has been reserved by ALSA. */
/* This is a physical address */
WRITEREG(dma_addr, BaseA1_in);
/* Define upper limit for DMA access */
WRITEREG(dma_addr + buffer_size, ProtA1_in);
} else {
printk(KERN_ERR
"aw2: snd_aw2_saa7146_pcm_init_capture: "
"Substream number is not 0 -> not managed\n");
}
}
//ISR(TIMER0_COMPA_vect){
void __vector_21(void){
count++;
if(count % 7800 == 0){ /*For 1 minute delay -> 1 min /0.025 (TIMER0_TIME - configured in the Timer inits ) = 40 time intervals*/
WRITEREG(PORTB, ~(1<<pinBit++)); /*PORT B is toggled and pinBit is increased*/
//PORTB = ~(1<<pinBit++);
count=0;
}
if(pinBit > lastLED) pinBit =0; /*when the lastLED is reached pinBit starts from 0*/
}
void snd_aw2_saa7146_pcm_trigger_stop_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
acon1 = READREG(ACON1);
if (stream_number == 0) {
/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
acon1 &= ~(3 * WS2_CTRL);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A2_OUT << 16), MC1);
} else if (stream_number == 1) {
/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
acon1 &= ~(3 * WS1_CTRL);
WRITEREG(acon1, ACON1);
WRITEREG((TR_E_A1_OUT << 16), MC1);
}
}
void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
acon1 = READREG(ACON1);
if (stream_number == 0) {
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
acon1 |= 2 * WS2_CTRL;
WRITEREG(acon1, ACON1);
} else if (stream_number == 1) {
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
acon1 |= 1 * WS1_CTRL;
WRITEREG(acon1, ACON1);
}
}
irqreturn_t snd_aw2_saa7146_interrupt(int irq, void *dev_id)
{
unsigned int isr;
unsigned int iicsta;
struct snd_aw2_saa7146 *chip = dev_id;
isr = READREG(ISR);
if (!isr)
return IRQ_NONE;
WRITEREG(isr, ISR);
if (isr & (IIC_S | IIC_E)) {
iicsta = READREG(IICSTA);
WRITEREG(0x100, IICSTA);
}
if (isr & A1_out) {
if (arr_substream_it_playback_cb[1].p_it_callback != NULL) {
arr_substream_it_playback_cb[1].
p_it_callback(arr_substream_it_playback_cb[1].
p_callback_param);
}
}
if (isr & A2_out) {
if (arr_substream_it_playback_cb[0].p_it_callback != NULL) {
arr_substream_it_playback_cb[0].
p_it_callback(arr_substream_it_playback_cb[0].
p_callback_param);
}
}
if (isr & A1_in) {
if (arr_substream_it_capture_cb[0].p_it_callback != NULL) {
arr_substream_it_capture_cb[0].
p_it_callback(arr_substream_it_capture_cb[0].
p_callback_param);
}
}
return IRQ_HANDLED;
}
void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
int stream_number)
{
unsigned int acon1 = 0;
/* In aw8 driver, dma transfert is always active. It is
started and stopped in a larger "space" */
acon1 = READREG(ACON1);
if (stream_number == 0) {
WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
/* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
acon1 |= 2 * WS2_CTRL;
WRITEREG(acon1, ACON1);
} else if (stream_number == 1) {
WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
/* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
acon1 |= 1 * WS1_CTRL;
WRITEREG(acon1, ACON1);
}
}
void init_interrupts(){
WRITEREG(PCICR,1<<PCIE2);
//PCICR = 1<< PCIE2;
/*
Bit 2 – PCIE2: Pin Change Interrupt Enable 1
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
*/
WRITEREG(PCMSK2, (1<<PCINT16 |1<<PCINT17 |1<<PCINT18 |1<<PCINT19 |1<<PCINT20 |1<<PCINT21 |1<<PCINT22 |1<<PCINT23));
//PCMSK2 = (1<<PCINT16 |1<<PCINT17 |1<<PCINT18 |1<<PCINT19 |1<<PCINT20 |1<<PCINT21 |1<<PCINT22 |1<<PCINT23);
/*
ENAABLE EXTENRNAL INTERRUPTS FOR ALL THE SWITCHES
Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23:16
Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
*/
}
int main( int argc, char const * const argv[] )
{
printf( "Hello, %s\n", argv[0] );
unsigned long const addr = ( 1 < argc ) ? strtoul(argv[1],0,0) : 0x28 ;
int fd = open( "/dev/mem", O_RDWR | O_SYNC);
if( 0 <= fd ){
map = (char *)mmap( 0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, I2CBASE );
if (map == (char*)-1 ) {
perror("mmap()");
exit(1);
}
WRITEREG(ISAR, addr);
char inBuf[80];
unsigned len = sizeof(inBuf);
long long const start = tickMs();
if( read( inBuf, len ) ){
printf( "read %u bytes in %llu ms\n", len, tickMs()-start );
for( unsigned i = 0 ; i < len ; i++ ){
printf( "%02x ", inBuf[i] );
}
printf( "\n" );
}
else
printf( "Error reading I2C data\n" );
// WRITEREG(ICR,ICR_RESET);
close( fd );
}
else
perror( "/dev/mem" );
return 0 ;
}
//Initialize function courtesy of Previous projects
void init_timer(){
/*------------------ Set TCCR0A values --------------------------
* Bit 7: COM0A1 = 0 Normal port operation. No Output Compare
* 6: COM0A0 = 0
* 5: COM0B1 = 0
* 4: COM0B0 = 0
* 3: unused = 0
* 2: unused = 0
* 1: WGM01 = 1 Sets Waveform Generation mode to CTC
* 0: WGM00 = 0
*/
WRITEREG(TCCR0A,1<<WGM01);
//TCCR0A = 1<<WGM01;
/*------------------ Set TCCR0B values --------------------------
* Bit 7: FOCOA = 0 Disable Force Output Compare
* 6: FOCOB = 0
* 5: unused = 0
* 4: unused = 0
* 3: WGM02 = 0 Sets Waveform Generation mode to CTC
* 2: CS02 = 1 Sets prescaler to 1024, I/O clock
* 1: CS01 = 0
* 0: CS00 = 1
*/
WRITEREG(TCCR0B,(1<<CS02 |1<<CS00));
//TCCR0B = (1<<CS02 |1<<CS00);
// Load Compare values for timer 0
WRITEREG(OCR0A,TIMER0_CNT);
//OCR0A = TIMER0_CNT;
WRITEREG(OCR0B,0); // not using this feature
//OCR0B = 0;
/*----------------- Set TIMSK0 values -------------------------
* Bit(s) 7-3: Unused = 0
* 2: OCIE0B = 0 Disable timer compare interrupt B
* 1: OCIE0A = 1 Enable timer compare interrupt A
* 0: TOIE0 = 0 Disable overflow interrupt
*/
WRITEREG(TIMSK0,1<<OCIE0A);
//TIMSK0 = 1<<OCIE0A;
/* Optional: Initialize timer to 0*/
WRITEREG(TCNT0,0);
//TCNT0 = 0;
}
ULONG MACH_CheckHW(void) {
static USHORT MACHList[]={0x4754,0x4755,0x475a,0x4757,
0x4756,0x4742,0x4744,0x4749,
0x4750,0x4751,0x4c49,0x4c42,
0x4c50,0x4c47,0x474d,0x4c4d};
ULONG i,rc,temp;
rc=pci_read_dword(&PciDevice,0,&temp);
if (rc) return RC_ERROR;
temp>>=16; //temp=PCI DEVICE ID
i=0;
while ((temp!=MACHList[i])&&(i<16)) i++;
if (i==16) return RC_ERROR;
rc=pci_read_dword(&PciDevice,0x10,&temp);
if (rc) return RC_ERROR;
temp&=0xfff00000;//mask out lower bits
MMIO=PhysToLin(temp+0x7ff800,0x800);
if (MMIO==NULL) return RC_ERROR;
//enable block 1 access
WaitForIdle(7);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,SCALER_COLOUR_CNTL, (0x00) | (0x10 << 8) | (0x10 << 16) );
WRITEREG(MMIO,SCALER_H_COEFF0, (0x00) | (0x20 << 8) );
WRITEREG(MMIO,SCALER_H_COEFF1, (0x0D) | (0x20 << 8) | (0x06 << 16) | (0x0D << 24) );
WRITEREG(MMIO,SCALER_H_COEFF2, (0x0D) | (0x1C << 8) | (0x0A << 16) | (0x0D << 24) );
WRITEREG(MMIO,SCALER_H_COEFF3, (0x0C) | (0x1A << 8) | (0x0E << 16) | (0x0C << 24) );
WRITEREG(MMIO,SCALER_H_COEFF4, (0x0C) | (0x14 << 8) | (0x14 << 16) | (0x0C << 24) );
pRegs->scale_cntl=0x0c; //filtering on, red temp=6500K
pRegs->chipflags|=MACH_NEED_RESETUP;
HideVideo=MACH_HideVideo;
VideoCaps=MACH_VideoCaps;
SetVideoAttr=MACH_SetVideoAttr;
GetVideoAttr=MACH_GetVideoAttr;
DisplayVideo=MACH_DisplayVideo;
SetupVideo=MACH_SetupVideo;
RestoreVideo=MACH_RestoreVideo;
return RC_SUCCESS;
}
void snd_aw2_saa7146_setup(struct snd_aw2_saa7146 *chip,
void __iomem *pci_base_addr)
{
unsigned int acon2;
unsigned int acon1 = 0;
int i;
chip->base_addr = pci_base_addr;
WRITEREG(0, IER);
WRITEREG((MRST_N << 16), MC1);
#ifdef __BIG_ENDIAN
acon1 |= A1_SWAP;
acon1 |= A2_SWAP;
#endif
acon1 |= 0 * WS1_CTRL;
acon1 |= 0 * WS2_CTRL;
acon1 |= 3 * WS4_CTRL;
acon1 |= 2 * WS3_CTRL;
acon1 |= 3 * AUDIO_MODE;
WRITEREG(acon1, ACON1);
WRITEREG(3 * (BurstA1_in) + 3 * (ThreshA1_in) +
3 * (BurstA1_out) + 3 * (ThreshA1_out) +
3 * (BurstA2_out) + 3 * (ThreshA2_out), PCI_BT_A);
WRITEREG((EAP << 16) | EAP, MC1);
WRITEREG((EI2C << 16) | EI2C, MC1);
WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
acon2 = A2_CLKSRC | BCLK1_OEN;
WRITEREG(acon2, ACON2);
snd_aw2_saa7146_use_digital_input(chip, 0);
for (i = 0; i < 8; ++i) {
WRITEREG(tsl1[i], TSL1 + (i * 4));
WRITEREG(tsl2[i], TSL2 + (i * 4));
}
}
void snd_aw2_saa7146_pcm_trigger_stop_capture(struct snd_aw2_saa7146 *chip,
int stream_number)
{
if (stream_number == 0)
WRITEREG((TR_E_A1_IN << 16), MC1);
}
ULONG MACH_HideVideo(void) {
WaitForIdle(4);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,OVERLAY_SCALE_CNTL,READREG(MMIO,OVERLAY_SCALE_CNTL)&0x3fffffff);
return RC_SUCCESS;
}
ULONG MACH_DisplayVideo(ULONG BufferOffset) {
if (!(pRegs->chipflags&MACH_NEED_RESETUP)) {
WaitForIdle(2);
WRITEREG(MMIO,BUS_CNTL,READREG(MMIO,BUS_CNTL)|BUS_CNTL_MASK);
WRITEREG(MMIO,SCALER_BUF0_OFFSET,BufferOffset);
pRegs->offset=BufferOffset;
return RC_SUCCESS;
}
WaitForIdle(12);
WRITEREG(MMIO,OVERLAY_SCALE_CNTL,pRegs->scale_cntl);
WRITEREG(MMIO,OVERLAY_SCALE_INC,pRegs->scale_inc);
WRITEREG(MMIO,VIDEO_FORMAT,pRegs->format);
WRITEREG(MMIO,SCALER_BUF0_PITCH,pRegs->pitch);
WRITEREG(MMIO,SCALER_HEIGHT_WIDTH,pRegs->height_width);
WRITEREG(MMIO,CAPTURE_CONFIG,pRegs->config);
WRITEREG(MMIO,OVERLAY_Y_X,pRegs->y_x);
WRITEREG(MMIO,OVERLAY_Y_X_END,pRegs->y_x_end);
WRITEREG(MMIO,SCALER_BUF0_OFFSET,BufferOffset);
pRegs->offset=BufferOffset;
WRITEREG(MMIO,OVERLAY_GRAPHICS_KEY_MSK,pRegs->key_msk);
WRITEREG(MMIO,OVERLAY_GRAPHICS_KEY_CLR,pRegs->key_clr);
WRITEREG(MMIO,OVERLAY_KEY_CNTL,pRegs->key_cntl);
pRegs->chipflags&=~MACH_NEED_RESETUP;
return RC_SUCCESS;
}
int DepthWriteMask(void)
{
unsigned int uDataSize;
#if 0
float box_obj0[] =
{
/* x y z w r g b a */
-0.1f, -0.1f, 1.0f, 1.0f, 1.0f, 0.0f, 0.0f, 0.5f,
0.1f, -0.1f, 1.0f, 1.0f, 1.0f, 0.0f, 0.0f, 0.5f,
-0.1f, 0.1f, 1.0f, 1.0f, 1.0f, 0.0f, 0.0f, 0.5f,
0.1f, 0.1f, 1.0f, 1.0f, 1.0f, 0.0f, 0.0f, 0.5f
};
float box_obj1[] =
{
/* x y z w r g b a */
0.0f, 0.0f, 0.5f, 1.0f, 1.0f, 1.0f, 0.0f, 0.5f,
0.2f, 0.0f, 0.5f, 1.0f, 1.0f, 1.0f, 0.0f, 0.5f,
0.0f, 0.2f, 0.5f, 1.0f, 1.0f, 1.0f, 0.0f, 0.5f,
0.2f, 0.2f, 0.5f, 1.0f, 1.0f, 1.0f, 0.0f, 0.5f
};
#endif
float VERTICES[2][6] =
{
{ 0.0f, 0.0f, 0.5f, 1.0f, 1.0f, 1.0f },
{ 0.0f, 0.0f, 0.75f, 0.0f, 0.0f, 0.0f }
};
if (fglLoadVShader(mov_v2o_vsa) != FGL_ERR_NO_ERROR) {
return ERROR;
}
if (fglLoadPShader(mov_v2o_psa) != FGL_ERR_NO_ERROR) {
return ERROR;
}
drvsys_clear_buf((unsigned int*)FIMG_DEPTH_BUFFER, CLEAR_SCREEN_SIZE, 0xFFFFFFFF);
drvsys_clear_buf((unsigned int*)(FIMG_COLOR_BUFFER), CLEAR_SCREEN_SIZE, 0x0);
fglFlush(FGL_PIPESTATE_ALL); // Pipeline status
// Vertex Shader SFR set
//WRITEREG(FGVS_ATTRIB_NUM, 0x00020002); // Attribute counter of VS input & output
//WRITEREG(FGVS_CONFIG, 0x00000001); // Configuration register
fglVSSetAttribNum(2);
// Pixel Shader SFR set
//WRITEREG(FGPS_EXE_MODE, 0x00000000); // Pixel shader execution mode control register
//WRITEREG(FGPS_PC_COPY, 0x00000001); // Copy PSPCS_ADDR value to program counter
//WRITEREG(FGPS_ATTRIB_NUM, 0x00000001); // Number of attribute of current context
//fglSysPollingMask(FGPS_INBUF_STATUS, 0x0, 0x00000001); // Status signal of pixel shader input buffer
//WRITEREG(FGPS_EXE_MODE, 0x00000001); // Pixel shader execution mode control register
fglPSSetAttributeNum(1);
// Depth write mask test main
{
// Primitive Engine SRF Set
FGL_Vertex Vtx;
Vtx.prim = FGL_PRIM_POINTS;
Vtx.enablePointSize = FGL_FALSE;
Vtx.numVSOut = 1;
Vtx.shadeModel = FGL_SHADING_SMOOTH;
Vtx.colorAttribIdx = 0;
fglSetVertex(&Vtx); // Vertex context register
//point size set
fglSetPointWidth(200.0f);
fglSetMinimumPointWidth(1.0f);
fglSetMaximumPointWidth(1024.0f);
// Depth/Stencil buffer base address
fglSetZBufBaseAddr(FIMG_DEPTH_BUFFER);
// Depth test function & enable set
if(fglSetDepthParams(FGL_COMP_LESS) != FGL_ERR_NO_ERROR) {
UART_Printf("\nDepth buffer test: The fglSetAlphaParams fial\n");
}
if(fglEnablePerFragUnit(FGL_PF_DEPTH, FGL_TRUE) != FGL_ERR_NO_ERROR) {
UART_Printf("\nDepth buffer test: The fglEnablePerFragUnit fial\n");
}
fglSetZBufWriteMask(FGL_TRUE);
FGL_HInterface HInterface;
HInterface.enableAutoInc = FGL_TRUE;
HInterface.enableVtxBuffer = FGL_FALSE;
HInterface.enableVtxCache = FGL_FALSE;
HInterface.idxType = FGL_INDEX_DATA_UINT;
HInterface.numVSOut = 2;
fglSetHInterface(&HInterface);
FGL_Attribute HIAttr;
HIAttr.bEndFlag = FGL_FALSE;
HIAttr.type = FGL_ATTRIB_DATA_FLOAT;
HIAttr.numComp = 3;
HIAttr.srcW = FGL_ATTRIB_ORDER_4TH;
HIAttr.srcZ = FGL_ATTRIB_ORDER_3RD;
HIAttr.srcY = FGL_ATTRIB_ORDER_2ND;
HIAttr.srcX = FGL_ATTRIB_ORDER_1ST;
fglSetAttribute(0, &HIAttr);
HIAttr.bEndFlag = FGL_TRUE;
fglSetAttribute(1, &HIAttr);
unsigned int uiTmpVertices = 1;
unsigned int uiDummy = 0xFFFFFFFF;
fglSendToFIFO(4, &uiTmpVertices);
fglSendToFIFO(4, &uiDummy);
uDataSize = sizeof(VERTICES)/sizeof(float)/2;
float *vtx = VERTICES[0];
fglSysTransferToPort(
(unsigned int *)vtx,
/*(volatile unsigned int *)(FGHI_FIFO_ENTRY),*/
uDataSize
);
fglFlush(FGL_PIPESTATE_ALL); // Pipeline status
fglSetPointWidth(100.0f);
fglSetZBufWriteMask(FGL_FALSE);
fglSendToFIFO(4, &uiTmpVertices);
fglSendToFIFO(4, &uiDummy);
vtx = VERTICES[1];
fglSysTransferToPort(
(unsigned int *)vtx,
/*(volatile unsigned int *)(FGHI_FIFO_ENTRY),*/
uDataSize
);
fglFlush(FGL_PIPESTATE_ALL); // Pipeline status
}
#if 0
// Per-fragment SFR set
// For Depth Test set to SFR
fglSysModifyReg(FGPF_DEPTH, 0x0000000E, (5<<1)|0x1); // Depth test mode: greater
WRITEREG(FGPF_DEPTHBUF_ADDR, FIMG_DEPTH_BUFFER); // Depth/Stencil buffer base address
WRITEREG(FGPF_DEPTH_MASK, 0x00000001); // Depth buffer write mask
// Host Interface SFR Set
FGL_HInterface HInterface;
HInterface.enableAutoInc = FGL_TRUE;
HInterface.enableVtxBuffer = FGL_FALSE;
HInterface.enableVtxCache = FGL_FALSE;
HInterface.idxType = FGL_INDEX_DATA_UINT;
HInterface.numVSOut = 2;
fglSetHInterface(&HInterface);
FGL_Attribute HIAttr;
HIAttr.bEndFlag = FGL_FALSE;
HIAttr.type = FGL_ATTRIB_DATA_FLOAT;
HIAttr.numComp = 4;
HIAttr.srcW = FGL_ATTRIB_ORDER_4TH;
HIAttr.srcZ = FGL_ATTRIB_ORDER_3RD;
HIAttr.srcY = FGL_ATTRIB_ORDER_2ND;
HIAttr.srcX = FGL_ATTRIB_ORDER_1ST;
fglSetAttribute(0, &HIAttr);
HIAttr.bEndFlag = FGL_TRUE;
fglSetAttribute(1, &HIAttr);
unsigned int uiTmpVertices = 4;
unsigned int uiDummy = 0xFFFFFFFF;
fglSendToFIFO(4, &uiTmpVertices);
fglSendToFIFO(4, &uiDummy);
uDataSize = sizeof(box_obj0)/sizeof(box_obj0[0]);
fglSysTransferToPort(
(unsigned int *)box_obj0,
/*(volatile unsigned int *)(FGHI_FIFO_ENTRY),*/
uDataSize
);
fglSysPollingMask(FG_PIPELINE_STATUS, 0x0, 0x00033717); // Pipeline status
// Per-fragment SFR set.
WRITEREG(FGPF_DEPTH_MASK, 0x00000000); // Depth buffer write mask
regval = ((5<<1)|0x1) & 0x0000000E;
WRITEREG(FGPF_LOGIC_OP, regval);
fglSendToFIFO(4, &uiTmpVertices);
fglSendToFIFO(4, &uiDummy);
uDataSize = sizeof(box_obj1)/sizeof(box_obj1[0]);
fglSysTransferToPort(
(unsigned int *)box_obj1,
/*(volatile unsigned int *)(FGHI_FIFO_ENTRY),*/
uDataSize
);
fglSysPollingMask(FG_PIPELINE_STATUS, 0x0, 0x00033717); // Pipeline status
WRITEREG(FGPF_DEPTH, 0x0); // Disable depth test
}
static bool read( char *data, // out
unsigned &len ) // in+out
{
unsigned const max = len ;
len = 0 ;
WRITEREG(ICR,ICR_RESET); //
WRITEREG(ISR,0x7ff); // ack interrupts
usleep(1000);
WRITEREG(ICR,ICR_SLENABLE);
CLRREGBIT(ICR,ICR_UR_BIT);
bool worked = false ;
for( unsigned i = 0 ; !worked && ( i < 1 ); i++ ){
long long start = tickMs();
do {
unsigned long isr = READREG(ISR);
if( isr & ISR_SAD ){
if( isr & ISR_MASTER_RX ){
printf( "Master rx\n" );
break ;
}
if( isr & ISR_SSD ){
// SETREGBIT(ISR,ISR_SSD_BIT);
printf( "Slave stop: no data\n" );
return true ;
}
if( isr & ISR_ACKNAK ){
// SETREGBIT(ISR,ISR_SSD_BIT);
printf( "nak waiting for slave\n" );
SETREGBIT(ISR,ISR_ACKNAKBIT);
return true ;
}
SETREGBIT(ISR,9);
worked = true ;
break ;
}
else if( isr & ISR_BED ){
printf( "bus error\n" );
break ;
}
long long now = tickMs();
if( now-start > 2000 ){
printf( "timeout waiting for slave\n" );
dumpRegs();
break ;
}
} while( 1 );
if( !worked ){
printf( "retry\n" );
WRITEREG(ICR,ICR_RESET); //
usleep((i+1)*1000);
CLRREGBIT(ICR,ICR_UR_BIT);
usleep((i+1)*1000);
WRITEREG(ICR,ICR_SLENABLE);
}
}
do {
SETREGBIT(ICR,ICR_TB_BIT);
long long start = tickMs();
do { // wait for rx
unsigned long isr = READREG(ISR);
if( isr & ISR_IRF ){
char const byte = READREG(IDBR);
data[len++] = byte ;
SETREGBIT(ISR,ISR_IRF_BIT); // ack
if( isr & ISR_SSD ){
// SETREGBIT(ISR,ISR_SSD_BIT);
return true ;
}
break ;
} else if( isr & ISR_SSD ){
return true ;
}
long long now = tickMs();
if( now-start > 2000 ){
printf( "timeout waiting for data\n" );
return false ;
}
} while( 1 );
} while( 1 );
return true ;
}
void snd_aw2_saa7146_setup(struct snd_aw2_saa7146 *chip,
void __iomem *pci_base_addr)
{
/* set PCI burst/threshold
Burst length definition
VALUE BURST LENGTH
000 1 Dword
001 2 Dwords
010 4 Dwords
011 8 Dwords
100 16 Dwords
101 32 Dwords
110 64 Dwords
111 128 Dwords
Threshold definition
VALUE WRITE MODE READ MODE
00 1 Dword of valid data 1 empty Dword
01 4 Dwords of valid data 4 empty Dwords
10 8 Dwords of valid data 8 empty Dwords
11 16 Dwords of valid data 16 empty Dwords */
unsigned int acon2;
unsigned int acon1 = 0;
int i;
/* Set base addr */
chip->base_addr = pci_base_addr;
/* disable all irqs */
WRITEREG(0, IER);
/* reset saa7146 */
WRITEREG((MRST_N << 16), MC1);
/* enable audio interface */
#ifdef __BIG_ENDIAN
acon1 |= A1_SWAP;
acon1 |= A2_SWAP;
#endif
/* WS0_CTRL, WS0_SYNC: input TSL1, I2S */
/* At initialization WS1 and WS2 are disabled (configured as input) */
acon1 |= 0 * WS1_CTRL;
acon1 |= 0 * WS2_CTRL;
/* WS4 is not used. So it must not restart A2.
This is why it is configured as output (force to low) */
acon1 |= 3 * WS4_CTRL;
/* WS3_CTRL, WS3_SYNC: output TSL2, I2S */
acon1 |= 2 * WS3_CTRL;
/* A1 and A2 are active and asynchronous */
acon1 |= 3 * AUDIO_MODE;
WRITEREG(acon1, ACON1);
/* The following comes from original windows driver.
It is needed to have a correct behavior of input and output
simultenously, but I don't know why ! */
WRITEREG(3 * (BurstA1_in) + 3 * (ThreshA1_in) +
3 * (BurstA1_out) + 3 * (ThreshA1_out) +
3 * (BurstA2_out) + 3 * (ThreshA2_out), PCI_BT_A);
/* enable audio port pins */
WRITEREG((EAP << 16) | EAP, MC1);
/* enable I2C */
WRITEREG((EI2C << 16) | EI2C, MC1);
/* enable interrupts */
WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
/* audio configuration */
acon2 = A2_CLKSRC | BCLK1_OEN;
WRITEREG(acon2, ACON2);
/* By default use analog input */
snd_aw2_saa7146_use_digital_input(chip, 0);
/* TSL setup */
for (i = 0; i < 8; ++i) {
WRITEREG(tsl1[i], TSL1 + (i * 4));
WRITEREG(tsl2[i], TSL2 + (i * 4));
}
}
void board_putc(char c)
{
while ((READREG(ASC_FSTAT) & TXMASK) >> TXOFFSET);
WRITEREG(ASC_TBUF, c);
}
