static void vbi_enable_lines(unsigned short start_line, unsigned short end_line, unsigned char data_type)
{
int i = 0;
/*@todo*/
if ((start_line < VBI_LINE_MIN)) {
if (vbi_dbg_en)
pr_info("[vbi..]: start line abnormal!!! line:%d \n", start_line);
start_line = VBI_LINE_MIN;
}
if ((end_line > VBI_LINE_MAX)) {
if (vbi_dbg_en)
pr_info("[vbi..]: end line abnormal!!! line:%d \n", end_line);
end_line = VBI_LINE_MAX;
}
for(i = VBI_LINE_MIN; i <= VBI_LINE_MAX ; i++) {
if ((i < start_line) || (i > end_line)){
WRITE_APB_REG((CVD2_VBI_DATA_TYPE_LINE7 + i - VBI_LINE_MIN), 0);
continue;
}
if (i == VBI_LINE_MIN) {
WRITE_APB_REG(CVD2_VBI_DATA_TYPE_LINE6, data_type);
} else {
WRITE_APB_REG((CVD2_VBI_DATA_TYPE_LINE7 + i - VBI_LINE_MIN), data_type);
if (vbi_dbg_en)
pr_info("[vbi..]: set line:%d type to 0x%x \n", i, data_type);
}
}
}
/**
* Write data to HDMI RX CTRL
* @param[in] addr register address
* @param[in] data new register value
*/
void hdmirx_wr_dwc(uint16_t addr, uint32_t data)
{
/* log_info("%04X:%08X", addr, data); */
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
WRITE_APB_REG((HDMIRX_DATA_PORT | dev_offset), data);
} /* hdmirx_wr_only_DWC */
void hdmi_wr_only_reg(unsigned long addr, unsigned long data)
{
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_DATA_PORT, data);
}
static unsigned int hdmi_rd_reg(unsigned long addr)
{
unsigned long data;
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
data = READ_APB_REG(HDMI_DATA_PORT);
return (data);
}
void tvafe_init_reg(struct tvafe_cvd2_s *cvd2, struct tvafe_cvd2_mem_s *mem, enum tvin_port_e port, struct tvafe_pin_mux_s *pinmux)
{
unsigned int i = 0;
if ((port >= TVIN_PORT_VGA0) && (port <= TVIN_PORT_VGA7))
{
/**enable auto mode clock**/
WRITE_CBUS_REG(HHI_TVFE_AUTOMODE_CLK_CNTL, 0x100);
/** write top register don't after write 7740 register**/
while (vga_top_reg_default[i][0] != 0xFFFFFFFF) {
WRITE_APB_REG(vga_top_reg_default[i][0], vga_top_reg_default[i][1]);
i++;
}
/** write 7740 register **/
tvafe_adc_configure(TVIN_SIG_FMT_VGA_1024X768P_60HZ_D004);
tvafe_top_config(TVIN_SIG_FMT_VGA_1024X768P_60HZ_D004);
}
else if ((port >= TVIN_PORT_COMP0) && (port <= TVIN_PORT_COMP7))
{
/**enable auto mode clock**/
WRITE_CBUS_REG(HHI_TVFE_AUTOMODE_CLK_CNTL, 0x100);
WRITE_CBUS_REG(HHI_VAFE_CLKOSCIN_CNTL, 0x100);
/** write top register don't after write 7740 register**/
while (comp_top_reg_default[i][0] != 0xFFFFFFFF) {
WRITE_APB_REG(comp_top_reg_default[i][0], comp_top_reg_default[i][1]);
i++;
}
/** write 7740 register **/
tvafe_adc_configure(TVIN_SIG_FMT_COMP_720P_59HZ_D940);
tvafe_top_config(TVIN_SIG_FMT_COMP_720P_59HZ_D940);
}
else if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_SVIDEO7))
{
#ifdef CRYSTAL_25M
WRITE_CBUS_REG(HHI_VAFE_CLKIN_CNTL, 0x703);
#endif
tvafe_set_cvbs_default(cvd2, mem, port, pinmux);
/*turn on/off av out*/
tvafe_enable_avout(enableavout);
}
/* must reload mux if you change adc reg table!!! */
tvafe_set_source_muxing(port, pinmux);
pr_info("[tvafe..] %s ok.\n", __func__);
}
void hdmirx_wr_top (unsigned long addr, unsigned long data)
{
ulong flags;
unsigned long dev_offset = 0; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
spin_lock_irqsave(®_rw_lock, flags);
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
WRITE_APB_REG((HDMIRX_DATA_PORT | dev_offset), data);
spin_unlock_irqrestore(®_rw_lock, flags);
if(hdmirx_log_flag & 0x2){
printk("Write TOP Reg 0x%08lx <= 0x%08lx\n", addr, data);
}
} /* hdmirx_wr_only_TOP */
static void turn_off_audio_DAC (void)
{
int wr_val;
wr_val = 0;
WRITE_APB_REG(ADAC_RESET, wr_val);
WRITE_APB_REG(ADAC_POWER_CTRL_REG1, wr_val);
WRITE_APB_REG(ADAC_POWER_CTRL_REG2, wr_val);
wr_val = 1;
WRITE_APB_REG(ADAC_LATCH, wr_val);
wr_val = 0;
WRITE_APB_REG(ADAC_LATCH, wr_val);
} /* turn_off_audio_DAC */
/**
* Write data to HDMI RX CTRL
* @param[in] addr register address
* @param[in] data new register value
*/
void hdmirx_wr_dwc(uint16_t addr, uint32_t data)
{
/* log_info("%04X:%08X", addr, data); */
ulong flags;
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
spin_lock_irqsave(®_rw_lock, flags);
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
WRITE_APB_REG((HDMIRX_DATA_PORT | dev_offset), data);
spin_unlock_irqrestore(®_rw_lock, flags);
if(hdmirx_log_flag & 0x2){
printk("Write DWC Reg 0x%08x <= 0x%08x\n", addr, data);
}
} /* hdmirx_wr_only_DWC */
static void hdmi_wr_reg(unsigned long addr, unsigned long data)
{
unsigned long rd_data;
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_DATA_PORT, data);
rd_data = hdmi_rd_reg (addr);
if (rd_data != data)
{
//while(1){};
}
}
void hdmi_wr_reg(unsigned long addr, unsigned long data)
{
unsigned long rd_data;
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_ADDR_PORT, addr);
WRITE_APB_REG(HDMI_DATA_PORT, data);
rd_data = hdmi_rd_reg (addr);
if (rd_data != data)
{
//printk("hdmi_wr_reg(%x,%x) fails to write: %x\n",addr, data, rd_data);
//while(1){};
}
}
void mute_headphone(void* codec, int flag)
{
int reg_val;
#ifdef _AML_M3_HW_DEBUG_
printk("***Entered %s:%s\n", __FILE__,__func__);
#endif
reg_val = READ_APB_REG(APB_BASE+(0x18<<2));
if(flag){
reg_val |= 0xc0;
WRITE_APB_REG((APB_BASE+(0x18<<2)), reg_val); // mute headphone
}else{
reg_val &= ~0xc0;
WRITE_APB_REG((APB_BASE+(0x18<<2)), reg_val); // unmute headphone
}
}
static void turn_off_audio_DAC(void)
{
int wr_val;
SET_CBUS_REG_MASK(HHI_GCLK_MPEG1, (1 << 13));//open ADC gate
wr_val = 0;
WRITE_APB_REG(ADAC_RESET, wr_val);
WRITE_APB_REG(ADAC_POWER_CTRL_REG1, wr_val);
WRITE_APB_REG(ADAC_POWER_CTRL_REG2, wr_val);
wr_val = 1;
WRITE_APB_REG(ADAC_LATCH, wr_val);
wr_val = 0;
WRITE_APB_REG(ADAC_LATCH, wr_val);
CLEAR_CBUS_REG_MASK(HHI_GCLK_MPEG1, (1 << 13));//close ADC gate
} /* turn_off_audio_DAC */
/**
* Read data from HDMI RX CTRL
* @param[in] addr register address
* @return data read value
*/
uint32_t hdmirx_rd_dwc(uint16_t addr)
{
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
return (data);
} /* hdmirx_rd_DWC */
unsigned long hdmirx_rd_top (unsigned long addr)
{
unsigned long dev_offset = 0; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
return (data);
} /* hdmirx_rd_TOP */
/**
* Read data from HDMI RX CTRL
* @param[in] addr register address
* @return data read value
*/
uint32_t hdmirx_rd_dwc(uint16_t addr)
{
ulong flags;
unsigned long dev_offset = 0x10; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
unsigned long data;
spin_lock_irqsave(®_rw_lock, flags);
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
data = READ_APB_REG((HDMIRX_DATA_PORT | dev_offset));
spin_unlock_irqrestore(®_rw_lock, flags);
return (data);
} /* hdmirx_rd_DWC */
static int aml_m1_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u16 *reg_cache = codec->reg_cache;
if (reg >= codec->reg_cache_size)
return -EINVAL;
WRITE_APB_REG((APB_BASE+(reg<<2)), value);
reg_cache[reg] = value;
return 0;
}
static void aml_audio_adc_power_gating(int flag)//flag=1 : on; flag=0 : off
{
u32 value;
value = READ_APB_REG(APB_ADAC_POWER_CTRL_REG2);
if(flag){
value |= 3;
}
else{
value &= ~3;
}
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, value);
}
static void vbi_hw_init(struct vbi_dev_s *devp)
{
WRITE_APB_REG(CVD2_VBI_DATA_TYPE_LINE21, 0x11);
WRITE_APB_REG(CVD2_VSYNC_VBI_LOCKOUT_START, 0x00000000);
WRITE_APB_REG(CVD2_VSYNC_VBI_LOCKOUT_END, 0x00000025);
WRITE_APB_REG(CVD2_VSYNC_TIME_CONSTANT, 0x0000004a);
WRITE_APB_REG(CVD2_VBI_CC_START, 0x00000054);
WRITE_APB_REG(CVD2_VBI_FRAME_CODE_CTL, 0x00000015);
}
static void aml_audio_clock_gating_disable(void)
{
struct snd_soc_codec* codec;
//printk("***Entered %s:%s\n", __FILE__,__func__);
//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)&~(1<<18));
WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)&~(1<<2)
//&~(0xFF<<6)
);
//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)&~(1<<10));
//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)&~(1<<10)
//&~(1<<18)
//&~(0x7<<14));
mute_spk(codec,1);
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)&(~(1<<7)));
adac_latch();
}
static void aml_audio_clock_gating_enable(void)
{
struct snd_soc_codec* codec;
printk("***Entered %s:%s\n", __FILE__,__func__);
//WRITE_CBUS_REG(HHI_GCLK_MPEG0, READ_CBUS_REG(HHI_GCLK_MPEG0)|(1<<18));
WRITE_CBUS_REG(HHI_GCLK_MPEG1, READ_CBUS_REG(HHI_GCLK_MPEG1)|(1<<2)
//|(0xFF<<6)
);
//WRITE_CBUS_REG(HHI_GCLK_MPEG2, READ_CBUS_REG(HHI_GCLK_MPEG2)|(1<<10));
//WRITE_CBUS_REG(HHI_GCLK_OTHER, READ_CBUS_REG(HHI_GCLK_OTHER)|(1<<10)
//|(1<<18)
//|(0x7<<14));
WRITE_APB_REG(APB_ADAC_POWER_CTRL_REG2, READ_APB_REG(APB_ADAC_POWER_CTRL_REG2)|(1<<7));
if(aml_m3_is_hp_pluged()){
mute_spk(codec,1);
}
else
mute_spk(codec,0);
adac_latch();
}
static void write_reg(char *para)
{
char count=2;
vout_reg_t reg;
memcpy(®, parse_para(para+1,&count), sizeof(vout_reg_t));
if (((*para) == 'm') || ((*para) == 'M')){
WRITE_MPEG_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", CBUS_REG_ADDR(reg.addr), reg.value, READ_MPEG_REG(reg.addr));
}
else if (((*para) == 'p') || ((*para) == 'P')) {
if (APB_REG_ADDR_VALID(reg.addr)){
WRITE_APB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", APB_REG_ADDR(reg.addr), reg.value, READ_APB_REG(reg.addr));
}
}
else if (((*para) == 'h') || ((*para) == 'H')) {
WRITE_AHB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", AHB_REG_ADDR(reg.addr), reg.value, READ_AHB_REG(reg.addr));
}
}
void cooling(void)
{
int i;
writel(0,P_WATCHDOG_TC);//disable Watchdog
//GPIOX_53 reset chip power ctrl
clrbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//vcc_12v/24v power down GPIOX_70
clrbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0);
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
while(1)
{
if(serial_tstc()) break;
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
/*
* rc 0x12345678
* rw 0x12345678 1234
* adress must be hexadecimal and prefix with ox.
*/
ssize_t vdin_dbg_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
char strcmd[16];
char straddr[10];
char strval[32];
int i = 0;
int j = 0;
unsigned long addr;
unsigned int value=0;
unsigned int retval;
/* get parameter command string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ') && (buf[i] != 10)){
strcmd[j] = buf[i];
i++;
j++;
}
strcmd[j] = '\0';
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
/* check address */
if (strncmp(&buf[i], "0x", 2) != 0){
pr_info("invalid parameter address\n");
tvin_dbg_usage();
return 32;
}
/* get parameter address string */
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ' && (buf[i] != 10))){
straddr[j] = buf[i];
i++;
j++;
}
straddr[j] = 0;
addr = simple_strtoul(straddr, NULL, 16); //hex data
/* rc read cbus */
if (strncmp(strcmd, "rc", 2) == 0){
retval = READ_CBUS_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* rp read apb */
else if (strncmp(strcmd, "rp", 2) == 0){
retval = READ_APB_REG(addr);
pr_info("%s: 0x%x --> 0x%x\n", strcmd, addr, retval);
return 32;
}
/* wc write cbus */
else if (strncmp(strcmd, "wc", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_CBUS_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
/* wp write apb */
else if (strncmp(strcmd, "wp", 2) == 0){
/* get parameter value string*/
/* ignore */
while( (i < count) && (buf[i]) && ((buf[i] ==',') || (buf[i] == ' ') || (buf[i] == 10))){
i++;
}
if (!buf[i]){
pr_info("no parameter value\n");
tvin_dbg_usage();
return 32;
}
j = 0;
while( (i < count) && (buf[i]) && (buf[i] != ',') && (buf[i] != ' ')&& (buf[i] != 10)){
strval[j] = buf[i];
i++;
j++;
}
strval[j] = '\0';
value = simple_strtol(strval, NULL, 16); //hex data
WRITE_APB_REG(addr, value);
pr_info("%s: 0x%x <-- 0x%x\n", strcmd, addr, value);
return 32;
}
else{
pr_info("invalid parameter\n");
tvin_dbg_usage();
return 32;
}
return 32;
}
static ssize_t store_dbg(struct device * dev, struct device_attribute *attr, const char * buf, size_t count)
{
char tmpbuf[128];
int i=0;
unsigned int adr;
unsigned int value=0;
while((buf[i])&&(buf[i]!=',')&&(buf[i]!=' ')){
tmpbuf[i]=buf[i];
i++;
}
tmpbuf[i]=0;
if(strncmp(tmpbuf, "config_dvin", 11)==0){
#ifdef DEBUG_DVIN
config_dvin (hs_pol_inv,
vs_pol_inv,
de_pol_inv,
field_pol_inv,
ext_field_sel,
de_mode,
data_comp_map,
mode_422to444,
dvin_clk_inv,
vs_hs_tim_ctrl,
hs_lead_vs_odd_min,
hs_lead_vs_odd_max,
active_start_pix_fe,
active_start_pix_fo,
active_start_line_fe,
active_start_line_fo,
line_width,
field_height);
#endif
}
else if(strncmp(tmpbuf, "pause", 5)==0){
hdmirx_device.task_pause = 1;
printk("Pause %s\n", __func__);
}
else if(strncmp(tmpbuf, "start", 5)==0){
hdmirx_device.task_pause = 0;
printk("Start %s\n", __func__);
}
else if(strncmp(tmpbuf, "spdif", 5)==0){
setHDMIRX_SPDIFOutput();
}
else if(strncmp(tmpbuf, "i2s", 3)==0){
setHDMIRX_I2SOutput(0x1);
}
else if(strncmp(tmpbuf, "hpd", 3)==0){
if(tmpbuf[3]=='0'){
CLEAR_HPD;
}
else if(tmpbuf[3]=='1'){
SET_HPD;
}
}
else if(tmpbuf[0]=='w'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
value=simple_strtoul(buf+i+1, NULL, 16);
if(buf[1]=='h'){
HDMIRX_WriteI2C_Byte(adr, value);
}
else if(buf[1]=='c'){
WRITE_MPEG_REG(adr, value);
pr_info("write %x to CBUS reg[%x]\n",value,adr);
}
else if(buf[1]=='p'){
WRITE_APB_REG(adr, value);
pr_info("write %x to APB reg[%x]\n",value,adr);
}
}
else if(tmpbuf[0]=='r'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
if(buf[1]=='h'){
value = HDMIRX_ReadI2C_Byte(adr);
pr_info("HDMI reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='c'){
value = READ_MPEG_REG(adr);
pr_info("CBUS reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='p'){
value = READ_APB_REG(adr);
pr_info("APB reg[%x]=%x\n", adr, value);
}
}
return 16;
}
void hdmirx_wr_top (unsigned long addr, unsigned long data)
{
unsigned long dev_offset = 0; // TOP ADDR_PORT: 0xc800e000; DWC ADDR_PORT: 0xc800e010
WRITE_APB_REG((HDMIRX_ADDR_PORT | dev_offset), addr);
WRITE_APB_REG((HDMIRX_DATA_PORT | dev_offset), data);
} /* hdmirx_wr_only_TOP */
void am_set_regmap(struct am_regs_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<p->length; i++) {
switch (p->am_reg[i].type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_CBUS_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_CBUS_REG(p->am_reg[i].addr, (READ_CBUS_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_APB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_APB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_APB_REG(p->am_reg[i].addr, (READ_APB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_MPEG:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_MPEG_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_MPEG_REG(p->am_reg[i].addr, (READ_MPEG_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AXI:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AXI_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AXI_REG(p->am_reg[i].addr, (READ_AXI_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AHB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AHB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AHB_REG(p->am_reg[i].addr, (READ_AHB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: chroma: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->am_reg[i].addr&0xf) == 0)||((p->am_reg[i].addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: coef: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
default:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->am_reg[i].type);
#endif
break;
}
}
return;
}
void cooling(void)
{
int i;
unsigned int tmp_data;
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = (void *)IO_APB_BUS_BASE,
.mmc_reg_base = (void *)APB_REG_ADDR(0x1000),
.hiu_reg_base = (void *)CBUS_REG_ADDR(0x1000),
.power_key = (1<<15),
.ddr_clk = 0x00120234, // 312m, 0x00110220, //384m
.sleepcount = 128,
//.set_vccx2 = set_vccx2, //Elvis Fool
.core_voltage_adjust = 5,
};
tvin_powerdown();
writel(0,P_WATCHDOG_TC);//disable Watchdog
//amp reset down GPIOX_51
clrbits_le32(P_PREG_FGPIO_O, 1<<19);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<19);
__udelay(1000);
//USB_PWR_CTL down x44
clrbits_le32(P_PREG_FGPIO_O, 1<<12);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<12);
//mute down x69
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl BL_EN
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//pwm x55
clrbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
setbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
setbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_48 LED_G
clrbits_le32(P_PREG_FGPIO_O, 1<<16);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<16);
//GPIOX_56 LED_R
setbits_le32(P_PREG_FGPIO_O, 1<<24);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<24);
//vcc_12v/24v power down GPIOX_70
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
serial_hw_init();
//setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0); //ENABLE: If this bit is set to 1, then the auto-clock ratio module will execute a change once the START pulses is generated.
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
/*
while(1)
{
if(serial_tstc()) break;
}*/
WRITE_CBUS_REG(0x2620, 0x10001);
WRITE_CBUS_REG(0x2621, 0x24);
WRITE_CBUS_REG(0x2622, 0);
WRITE_CBUS_REG(0x2623, 0);
WRITE_CBUS_REG(0x2624, 0);
enable_custom_trigger();
#ifdef CONFIG_MACH_MESON2_7366M_CST02
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
#ifdef CONFIG_MACH_MESON2_7366M_REFE03
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
tmp_data = READ_CBUS_REG(PREG_CTLREG0_ADDR);
WRITE_CBUS_REG(PREG_CTLREG0_ADDR, tmp_data | 0x1);
tmp_data = READ_CBUS_REG(IR_DEC_REG0);
WRITE_CBUS_REG(IR_DEC_REG0, tmp_data & 0xFFFFFF00);
tmp_data = READ_CBUS_REG(IR_DEC_REG1);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data | 0x00000001);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data & 0xFFFFFFFE);
//hub reset down x50
clrbits_le32(P_PREG_FGPIO_O, 1<<18);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<18);
//GPIOX_32 si2176_RESET down
clrbits_le32(P_PREG_FGPIO_O, 1<<0);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<0);
//PHY_RESET x57
clrbits_le32(P_PREG_FGPIO_O, 1<<25);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<25);
//close ddr
//gpiob_8
setbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
setbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//setbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
for(i=0; i<100; i++)
{
__udelay(1000);
}
meson_cpu_suspend(aml_pm_pdata);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_54 reset chip panel power
clrbits_le32(P_PREG_FGPIO_O, 1<<22);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<22);
//pwm x55
setbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
clrbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
clrbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<300; i++)
{
__udelay(1000);
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
//setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
void am_set_regmap(unsigned int cnt, struct am_reg_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<cnt; i++) {
switch (p->type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->mask == 0xffffffff)
WRITE_CBUS_REG(p->addr, p->val);
else
WRITE_CBUS_REG(p->addr, (READ_CBUS_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_APB:
if (p->mask == 0xffffffff)
WRITE_APB_REG(p->addr, p->val);
else
WRITE_APB_REG(p->addr, (READ_APB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb bus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_MPEG:
if (p->mask == 0xffffffff)
WRITE_MPEG_REG(p->addr, p->val);
else
WRITE_MPEG_REG(p->addr, (READ_MPEG_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AXI:
if (p->mask == 0xffffffff)
WRITE_AXI_REG(p->addr, p->val);
else
WRITE_AXI_REG(p->addr, (READ_AXI_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AHB:
if (p->mask == 0xffffffff)
WRITE_AHB_REG(p->addr, p->val);
else
WRITE_AHB_REG(p->addr, (READ_AHB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
if (p->mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~p->mask)) | (p->val & p->mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppchroma: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->addr&0xf) == 0)||((p->addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppcoef: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
default:
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->type);
break;
}
p++;
}
return;
}
void adac_wr_reg (unsigned long addr, unsigned long data)
{
WRITE_APB_REG((APB_BASE+(addr<<2)), data);
//acodec_regbank[addr] = data;
} /* adac_wr_reg */
void analog_switch(int flag)
{
int i;
unsigned reg_value = 0;
if (flag) {
printf("analog on\n");
SET_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 1 to power on top analog
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
WRITE_CBUS_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 2) {
WRITE_APB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 3) {
WRITE_AHB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
}
}
}
} else {
printf("analog off\n");
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
analog_regs[i].reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, CBUS_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 2) {
analog_regs[i].reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, APB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 3) {
analog_regs[i].reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, AHB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
}
}
}
CLEAR_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 0 to shutdown top analog
}
}