BX_CPU_C::write_RMW_virtual_word(Bit16u val16) { if (BX_CPU_THIS_PTR address_xlation.pages > 2) { // Pages > 2 means it stores a host address for direct access. Bit16u *hostAddr = (Bit16u *) BX_CPU_THIS_PTR address_xlation.pages; WriteHostWordToLittleEndian(hostAddr, val16); } else if (BX_CPU_THIS_PTR address_xlation.pages == 1) { BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1, 2, &val16); } else { #ifdef BX_LITTLE_ENDIAN BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1, 1, &val16); BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2, 1, ((Bit8u *) &val16) + 1); #else BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress1, 1, ((Bit8u *) &val16) + 1); BX_CPU_THIS_PTR mem->writePhysicalPage(BX_CPU_THIS, BX_CPU_THIS_PTR address_xlation.paddress2, 1, &val16); #endif } }
BX_CPU_C::write_virtual_word(unsigned s, bx_address offset, Bit16u data) { bx_address laddr; bx_segment_reg_t *seg = &BX_CPU_THIS_PTR sregs[s]; BX_INSTR_MEM_DATA_ACCESS(BX_CPU_ID, s, offset, 2, BX_WRITE); if (seg->cache.valid & SegAccessWOK4G) { accessOK: laddr = BX_CPU_THIS_PTR get_laddr(s, offset); #if BX_SupportGuest2HostTLB unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1); bx_address lpf = AlignedAccessLPFOf(laddr, 1); bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex]; if (tlbEntry->lpf == lpf) { // See if the TLB entry privilege level allows us write access // from this CPL. if (tlbEntry->accessBits & (0x10 << CPL)) { bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE); BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, CPL, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); #if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); #endif WriteHostWordToLittleEndian(hostAddr, data); return; } } #endif #if BX_SUPPORT_X86_64 if (! IsCanonical(laddr)) { BX_ERROR(("write_virtual_word(): canonical failure")); exception(int_number(seg), 0, 0); } #endif #if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK if (BX_CPU_THIS_PTR alignment_check()) { if (laddr & 1) { BX_ERROR(("write_virtual_word(): #AC misaligned access")); exception(BX_AC_EXCEPTION, 0, 0); } } #endif access_write_linear(laddr, 2, CPL, (void *) &data); return; } if (seg->cache.valid & SegAccessWOK) { if (Is64BitMode() || (offset < seg->cache.u.segment.limit_scaled)) goto accessOK; } write_virtual_checks(seg, offset, 2); goto accessOK; }
// assuming the write happens in legacy mode void BX_CPU_C::write_new_stack_word_32(bx_segment_reg_t *seg, bx_address offset, unsigned curr_pl, Bit16u data) { Bit32u laddr; BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64); if (seg->cache.valid & SegAccessWOK4G) { accessOK: laddr = (Bit32u)(seg->cache.u.segment.base + offset); #if BX_SupportGuest2HostTLB unsigned tlbIndex = BX_TLB_INDEX_OF(laddr, 1); bx_address lpf = AlignedAccessLPFOf(laddr, 1); bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[tlbIndex]; if (tlbEntry->lpf == lpf) { // See if the TLB entry privilege level allows us write access // from this CPL. if (tlbEntry->accessBits & (0x10 << CPL)) { bx_hostpageaddr_t hostPageAddr = tlbEntry->hostPageAddr; Bit32u pageOffset = PAGE_OFFSET(laddr); BX_INSTR_LIN_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, BX_WRITE); BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, laddr, tlbEntry->ppf | pageOffset, 2, curr_pl, BX_WRITE, (Bit8u*) &data); Bit16u *hostAddr = (Bit16u*) (hostPageAddr | pageOffset); #if BX_SUPPORT_ICACHE pageWriteStampTable.decWriteStamp(tlbEntry->ppf); #endif WriteHostWordToLittleEndian(hostAddr, data); return; } } #endif #if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK if (BX_CPU_THIS_PTR alignment_check() && curr_pl == 3) { if (laddr & 1) { BX_ERROR(("write_new_stack_word_32(): #AC misaligned access")); exception(BX_AC_EXCEPTION, 0, 0); } } #endif access_write_linear(laddr, 2, curr_pl, (void *) &data); return; } if (seg->cache.valid & SegAccessWOK) { if (offset < seg->cache.u.segment.limit_scaled) goto accessOK; } write_virtual_checks(seg, offset, 2); goto accessOK; }
BX_CPU_C::write_virtual_word(unsigned s, bx_address offset, Bit16u *data) { bx_address laddr; bx_segment_reg_t *seg; seg = &BX_CPU_THIS_PTR sregs[s]; if (seg->cache.valid & SegAccessWOK) { if ((Is64BitMode() && IsCanonical(offset)) || (offset < seg->cache.u.segment.limit_scaled)) { unsigned pl; accessOK: laddr = BX_CPU_THIS_PTR get_segment_base(s) + offset; BX_INSTR_MEM_DATA(BX_CPU_ID, laddr, 2, BX_WRITE); pl = (CPL==3); #if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK if (pl && BX_CPU_THIS_PTR alignment_check) { if (laddr & 1) { BX_ERROR(("write_virtual_word(): misaligned access")); exception(BX_AC_EXCEPTION, 0, 0); } } #endif #if BX_SupportGuest2HostTLB Bit16u *hostAddr = v2h_write_word(laddr, pl); if (hostAddr) { // Current write access has privilege. WriteHostWordToLittleEndian(hostAddr, *data); return; } #endif access_linear(laddr, 2, pl, BX_WRITE, (void *) data); return; } } write_virtual_checks(seg, offset, 2); goto accessOK; }