void WriteReg(u32 addr,u32 data)
{
if (addr < 0x2000)
{
//Channel data
u32 chan=addr>>7;
u32 reg=addr&0x7F;
if (sz==1)
{
WriteMemArr(aica_reg,addr,data,1);
WriteChannelReg8(chan,reg);
}
else
{
WriteMemArr(aica_reg,addr,data,2);
WriteChannelReg8(chan,reg);
WriteChannelReg8(chan,reg+1);
}
return;
}
void WriteAicaReg(u32 reg,u32 data)
{
switch (reg)
{
case SCIPD_addr:
verify(sz!=1);
if (data & (1<<5))
{
SCIPD->SCPU=1;
update_arm_interrupts();
}
//Read only
return;
case SCIRE_addr:
{
verify(sz!=1);
SCIPD->full&=~(data /*& SCIEB->full*/ ); //is the & SCIEB->full needed ? doesn't seem like it
data=0;//Write only
update_arm_interrupts();
}
break;
case MCIPD_addr:
if (data & (1<<5))
{
verify(sz!=1);
MCIPD->SCPU=1;
UpdateSh4Ints();
}
//Read only
return;
case MCIRE_addr:
{
verify(sz!=1);
MCIPD->full&=~data;
UpdateSh4Ints();
//Write only
}
break;
case TIMER_A:
WriteMemArr(aica_reg,reg,data,sz);
timers[0].RegisterWrite();
break;
case TIMER_B:
WriteMemArr(aica_reg,reg,data,sz);
timers[1].RegisterWrite();
break;
case TIMER_C:
WriteMemArr(aica_reg,reg,data,sz);
timers[2].RegisterWrite();
break;
default:
WriteMemArr(aica_reg,reg,data,sz);
break;
}
}
