/** This function does the necessary initialization of PCAP interface
*
* @param None
*
* @return error status based on implemented functionality (SUCCESS by default)
*
*****************************************************************************/
u32 XFsbl_PcapInit(void) {
u32 RegVal;
u32 Status = XFSBL_SUCCESS;
/* Take PCAP out of Reset */
RegVal = XFsbl_In32(CSU_PCAP_RESET);
RegVal &= (~CSU_PCAP_RESET_RESET_MASK);
XFsbl_Out32(CSU_PCAP_RESET, RegVal);
/* Select PCAP mode and change PCAP to write mode */
RegVal = CSU_PCAP_CTRL_PCAP_PR_MASK;
XFsbl_Out32(CSU_PCAP_CTRL, RegVal);
XFsbl_Out32(CSU_PCAP_RDWR, 0x0);
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_PL_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_PL_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_PL_POWER_UP\r\n");
goto END;
}
/* Reset PL */
XFsbl_Out32(CSU_PCAP_PROG, 0x0U);
usleep(PL_RESET_PERIOD_IN_US);
XFsbl_Out32(CSU_PCAP_PROG, CSU_PCAP_PROG_PCFG_PROG_B_MASK);
/*
* Wait for PL_init completion
* Bypass this check in platforms not supporting PCAP interface
*/
if ((XFSBL_PLATFORM != XFSBL_PLATFORM_REMUS)
&& (XFSBL_PLATFORM != XFSBL_PLATFORM_QEMU)) {
RegVal = 0U;
do {
RegVal = XFsbl_In32(CSU_PCAP_STATUS) &
CSU_PCAP_STATUS_PL_INIT_MASK;
} while (RegVal != CSU_PCAP_STATUS_PL_INIT_MASK);
} else {
XFsbl_Printf(DEBUG_GENERAL,
"PCAP interface is not supported in this platform \r\n");
}
END:
return Status;
}
static u32 XFsbl_SetCpuPwrSettings (u32 CpuSettings, u32 Flags)
{
u32 RegValue;
u32 Status;
u32 CpuId;
u32 ExecState;
u32 PwrStateMask;
/**
* Reset the CPU
*/
if ((Flags & XFSBL_CPU_SWRST) != 0U)
{
CpuId = CpuSettings & XIH_PH_ATTRB_DEST_CPU_MASK;
ExecState = CpuSettings & XIH_PH_ATTRB_A53_EXEC_ST_MASK;
switch(CpuId)
{
case XIH_PH_ATTRB_DEST_CPU_A53_0:
PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU0_MASK |
PMU_GLOBAL_PWR_STATE_FP_MASK |
PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_A53_0_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_A53_0_POWER_UP\r\n");
goto END;
}
/**
* Set to Aarch32 if enabled
*/
if (ExecState == XIH_PH_ATTRB_A53_EXEC_ST_AA32)
{
RegValue = XFsbl_In32(APU_CONFIG_0);
RegValue &= ~(APU_CONFIG_0_AA64N32_MASK_CPU0);
XFsbl_Out32(APU_CONFIG_0, RegValue);
}
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
/**
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU0_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU0_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_A53_1:
PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU1_MASK |
PMU_GLOBAL_PWR_STATE_FP_MASK |
PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_A53_1_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_A53_1_POWER_UP\r\n");
goto END;
}
/**
* Set to Aarch32 if enabled
*/
if (ExecState == XIH_PH_ATTRB_A53_EXEC_ST_AA32)
{
RegValue = XFsbl_In32(APU_CONFIG_0);
RegValue &= ~(APU_CONFIG_0_AA64N32_MASK_CPU1);
XFsbl_Out32(APU_CONFIG_0, RegValue);
}
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
/**
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU1_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU1_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_A53_2:
PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU2_MASK |
PMU_GLOBAL_PWR_STATE_FP_MASK |
PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_A53_2_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_A53_2_POWER_UP\r\n");
goto END;
}
/**
* Set to Aarch32 if enabled
*/
if (ExecState == XIH_PH_ATTRB_A53_EXEC_ST_AA32)
{
RegValue = XFsbl_In32(APU_CONFIG_0);
RegValue &= ~(APU_CONFIG_0_AA64N32_MASK_CPU2);
XFsbl_Out32(APU_CONFIG_0, RegValue);
}
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
/**
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU2_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU2_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_A53_3:
PwrStateMask = PMU_GLOBAL_PWR_STATE_ACPU3_MASK |
PMU_GLOBAL_PWR_STATE_FP_MASK |
PMU_GLOBAL_PWR_STATE_L2_BANK0_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_A53_3_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_A53_3_POWER_UP\r\n");
goto END;
}
/**
* Set to Aarch32 if enabled
*/
if (ExecState == XIH_PH_ATTRB_A53_EXEC_ST_AA32)
{
RegValue = XFsbl_In32(APU_CONFIG_0);
RegValue &= ~(APU_CONFIG_0_AA64N32_MASK_CPU3);
XFsbl_Out32(APU_CONFIG_0, RegValue);
}
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRF_APB_ACPU_CTRL);
RegValue |= (CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |
CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK);
XFsbl_Out32(CRF_APB_ACPU_CTRL, RegValue);
/**
* Release reset
*/
RegValue = XFsbl_In32(CRF_APB_RST_FPD_APU);
RegValue &= ~(CRF_APB_RST_FPD_APU_ACPU3_RESET_MASK |
CRF_APB_RST_FPD_APU_APU_L2_RESET_MASK |
CRF_APB_RST_FPD_APU_ACPU3_PWRON_RESET_MASK);
XFsbl_Out32(CRF_APB_RST_FPD_APU, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_R5_0:
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_R5_0_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_0_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_0_POWER_UP\r\n");
goto END;
}
/**
* Place R5, TCM's in split mode
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue |= (RPU_RPU_GLBL_CNTL_SLSPLIT_MASK);
RegValue &= ~(RPU_RPU_GLBL_CNTL_TCM_COMB_MASK);
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLCLAMP_MASK);
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-0 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue &= ~(RPU_RPU_0_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= (CRL_APB_CPU_R5_CTRL_CLKACT_MASK);
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void)usleep(0x50U);
/**
* Release reset to R5-0
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
/**
* Take R5-0 out of HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue |= RPU_RPU_0_CFG_NCPUHALT_MASK;
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_R5_1:
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_R5_1_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_1_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_1_POWER_UP\r\n");
goto END;
}
/**
* Place R5, TCM's in split mode
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue |= RPU_RPU_GLBL_CNTL_SLSPLIT_MASK;
RegValue &= ~(RPU_RPU_GLBL_CNTL_TCM_COMB_MASK);
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLCLAMP_MASK);
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-1 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue &= ~(RPU_RPU_1_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= CRL_APB_CPU_R5_CTRL_CLKACT_MASK;
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void)usleep(0x50U);
/**
* Release reset to R5-1
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
/**
* Take R5-1 out of HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue |= RPU_RPU_1_CFG_NCPUHALT_MASK;
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
break;
case XIH_PH_ATTRB_DEST_CPU_R5_L:
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_R5_0_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_L_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_L_POWER_UP\r\n");
goto END;
}
/**
* Place R5, TCM's in safe mode
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLSPLIT_MASK);
RegValue |= RPU_RPU_GLBL_CNTL_TCM_COMB_MASK;
RegValue |= RPU_RPU_GLBL_CNTL_SLCLAMP_MASK;
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-0 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue &= ~(RPU_RPU_0_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
/**
* Place R5-1 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue &= ~(RPU_RPU_1_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= CRL_APB_CPU_R5_CTRL_CLKACT_MASK;
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void )usleep(0x50U);
/**
* Release reset to R5-0, R5-1
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
/**
* Take R5-0 out of HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue |= RPU_RPU_0_CFG_NCPUHALT_MASK;
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
/**
* Take R5-1 out of HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue |= RPU_RPU_1_CFG_NCPUHALT_MASK;
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
break;
default:
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_HANDOFF_CPUID\n\r");
Status = XFSBL_ERROR_HANDOFF_CPUID;
break;
}
}
else
{
Status = XFSBL_SUCCESS;
}
END:
return Status;
}
/**
* This function checks the power state and reset for the memory type
* and release the reset if required
*
* @param MemoryType is the memory to be checked
* - XFSBL_R5_0_TCM
* - XFSBL_R5_1_TCM
* (to be added)
* - XFSBL_R5_0_TCMA
* - XFSBL_R5_0_TCMB
* - XFSBL_PS_DDR
* - XFSBL_PL_DDR
*
* @return none
*****************************************************************************/
static u32 XFsbl_PowerUpMemory(u32 MemoryType)
{
u32 RegValue;
u32 Status = XFSBL_SUCCESS;
u32 PwrStateMask;
/**
* Check the power status of the memory
* Power up if required
*
* Release the reset of the memory if present
*/
switch (MemoryType)
{
case XFSBL_R5_0_TCM:
{
PwrStateMask = PMU_GLOBAL_PWR_STATE_R5_0_MASK |
PMU_GLOBAL_PWR_STATE_TCM0A_MASK |
PMU_GLOBAL_PWR_STATE_TCM0B_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_0_TCM_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_0_TCM_POWER_UP\r\n");
goto END;
}
/**
* To access TCM,
* Release reset to R5 and enable the clk
* R5 is under halt state
*
* If R5 are out of reset and clk is enabled so doing
* again is no issue. R5 might be under running state
*/
/**
* Place R5, TCM in split mode
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue |= RPU_RPU_GLBL_CNTL_SLSPLIT_MASK;
RegValue &= ~(RPU_RPU_GLBL_CNTL_TCM_COMB_MASK);
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLCLAMP_MASK);
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-0 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue &= ~(RPU_RPU_0_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= CRL_APB_CPU_R5_CTRL_CLKACT_MASK;
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void)usleep(0x50U);
/**
* Release reset to R5-0
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
} break;
case XFSBL_R5_1_TCM:
{
PwrStateMask = PMU_GLOBAL_PWR_STATE_R5_1_MASK |
PMU_GLOBAL_PWR_STATE_TCM1A_MASK |
PMU_GLOBAL_PWR_STATE_TCM1B_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_1_TCM_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_1_TCM_POWER_UP\r\n");
goto END;
}
/**
* Place R5 in split mode
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue |= RPU_RPU_GLBL_CNTL_SLSPLIT_MASK;
RegValue &= ~(RPU_RPU_GLBL_CNTL_TCM_COMB_MASK);
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLCLAMP_MASK);
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-1 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue &= ~(RPU_RPU_1_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= CRL_APB_CPU_R5_CTRL_CLKACT_MASK;
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void )usleep(0x50U);
/**
* Release reset to R5-1
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
} break;
case XFSBL_R5_L_TCM:
{
PwrStateMask = PMU_GLOBAL_PWR_STATE_R5_0_MASK |
PMU_GLOBAL_PWR_STATE_TCM0A_MASK |
PMU_GLOBAL_PWR_STATE_TCM0B_MASK |
PMU_GLOBAL_PWR_STATE_TCM1A_MASK |
PMU_GLOBAL_PWR_STATE_TCM1B_MASK;
Status = XFsbl_PowerUpIsland(PwrStateMask);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_R5_L_TCM_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_R5_L_TCM_POWER_UP\r\n");
goto END;
}
/**
* Place R5 in lock step mode
* Combine TCM's
*/
RegValue = XFsbl_In32(RPU_RPU_GLBL_CNTL);
RegValue |= RPU_RPU_GLBL_CNTL_SLCLAMP_MASK;
RegValue &= ~(RPU_RPU_GLBL_CNTL_SLSPLIT_MASK);
RegValue |= RPU_RPU_GLBL_CNTL_TCM_COMB_MASK;
XFsbl_Out32(RPU_RPU_GLBL_CNTL, RegValue);
/**
* Place R5-0 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_0_CFG);
RegValue &= ~(RPU_RPU_0_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_0_CFG, RegValue);
/**
* Place R5-1 in HALT state
*/
RegValue = XFsbl_In32(RPU_RPU_1_CFG);
RegValue &= ~(RPU_RPU_1_CFG_NCPUHALT_MASK);
XFsbl_Out32(RPU_RPU_1_CFG, RegValue);
/**
* Enable the clock
*/
RegValue = XFsbl_In32(CRL_APB_CPU_R5_CTRL);
RegValue |= CRL_APB_CPU_R5_CTRL_CLKACT_MASK;
XFsbl_Out32(CRL_APB_CPU_R5_CTRL, RegValue);
/**
* Provide some delay,
* so that clock propogates properly.
*/
(void )usleep(0x50U);
/**
* Release reset to R5-0,R5-1
*/
RegValue = XFsbl_In32(CRL_APB_RST_LPD_TOP);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R50_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_R51_RESET_MASK);
RegValue &= ~(CRL_APB_RST_LPD_TOP_RPU_AMBA_RESET_MASK);
XFsbl_Out32(CRL_APB_RST_LPD_TOP, RegValue);
} break;
default:
/* nothing to do */
break;
}
END:
return Status;
}
/**
* This function initializes the system using the psu_init()
*
* @param FsblInstancePtr is pointer to the XFsbl Instance
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
******************************************************************************/
static u32 XFsbl_SystemInit(XFsblPs * FsblInstancePtr)
{
u32 Status = XFSBL_SUCCESS;
#if defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR) && !defined (ARMR5)
u32 BlockNum;
#endif
/**
* MIO33 can be used to control power to PL through PMU.
* For 1.0 and 2.0 Silicon, a workaround is needed to Powerup PL
* before MIO33 is configured. Hence, before MIO configuration,
* Powerup PL (but restore isolation).
*/
if (XGetPSVersion_Info() <= XPS_VERSION_2) {
Status = XFsbl_PowerUpIsland(PMU_GLOBAL_PWR_STATE_PL_MASK);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_PL_POWER_UP;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_PL_POWER_UP\r\n");
goto END;
}
/* For PS only reset, make sure FSBL exits with isolation removed */
if (FsblInstancePtr->ResetReason != PS_ONLY_RESET) {
XFsbl_IsolationRestore(PMU_GLOBAL_REQ_ISO_INT_EN_PL_NONPCAP_MASK);
}
}
/**
* psu initialization
*/
Status = (u32)psu_init();
if (XFSBL_SUCCESS != Status) {
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_PSU_INIT_FAILED\n\r");
/**
* Need to check a way to communicate both FSBL code
* and PSU init error code
*/
Status = XFSBL_PSU_INIT_FAILED + Status;
goto END;
}
#ifdef XFSBL_PERF
XTime_GetTime(&(FsblInstancePtr->PerfTime.tFsblStart));
#endif
#if defined (XPAR_PSU_DDR_0_S_AXI_BASEADDR) && !defined (ARMR5)
/* For A53, mark DDR region as "Memory" as DDR initialization is done */
#ifdef ARMA53_64
/* For A53 64bit*/
for(BlockNum = 0; BlockNum < NUM_BLOCKS_A53_64; BlockNum++)
{
XFsbl_SetTlbAttributes(BlockNum * BLOCK_SIZE_A53_64, ATTRIB_MEMORY_A53_64);
}
Xil_DCacheFlush();
#else
/* For A53 32bit*/
for(BlockNum = 0; BlockNum < NUM_BLOCKS_A53_32; BlockNum++)
{
XFsbl_SetTlbAttributes(BlockNum * BLOCK_SIZE_A53_32, ATTRIB_MEMORY_A53_32);
}
Xil_DCacheFlush();
#endif
#endif
/**
* Forcing the SD card detection signal to bypass the debouncing logic.
* This will ensure that SD controller doesn't end up waiting for long,
* fixed durations for card to be stable.
*/
XFsbl_Out32(IOU_SLCR_SD_CDN_CTRL,
(IOU_SLCR_SD_CDN_CTRL_SD1_CDN_CTRL_MASK |
IOU_SLCR_SD_CDN_CTRL_SD0_CDN_CTRL_MASK));
/**
* DDR Check if present
*/
/**
* Poweroff the unused blocks as per PSU
*/
END:
return Status;
}
